/** @file
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Data format for Universal Data Structure
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@copyright
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Copyright 1999 - 2021 Intel Corporation. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _IIO_UNIVERSAL_DATA_
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#define _IIO_UNIVERSAL_DATA_
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#define IIO_UNIVERSAL_DATA_GUID { 0x7FF396A1, 0xEE7D, 0x431E, { 0xBA, 0x53, 0x8F, 0xCA, 0x12, 0x7C, 0x44, 0xC0 } }
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#include "SysHost.h"
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#include "IioPlatformData.h"
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#include "UncoreCommonIncludes.h"
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#include <Guid/SocketVariable.h>
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//--------------------------------------------------------------------------------------//
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// Structure definitions for Universal Data Store (UDS)
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//--------------------------------------------------------------------------------------//
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#define UINT64 unsigned long long
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#pragma pack(1)
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typedef struct {
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UINT8 Valid; // TRUE, if the link is valid (i.e reached normal operation)
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UINT8 PeerSocId; // Socket ID
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UINT8 PeerSocType; // Socket Type (0 - CPU; 1 - IIO)
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UINT8 PeerPort; // Port of the peer socket
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}QPI_PEER_DATA;
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typedef struct {
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UINT8 Valid;
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UINT32 MmioBar[TYPE_MAX_MMIO_BAR];
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UINT8 PcieSegment;
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UINT64_STRUCT SegMmcfgBase;
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UINT16 stackPresentBitmap;
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UINT16 M2PciePresentBitmap;
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UINT8 TotM3Kti;
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UINT8 TotCha;
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UINT32 ChaList[MAX_CHA_MAP];
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UINT32 SocId;
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QPI_PEER_DATA PeerInfo[MAX_FW_KTI_PORTS]; // QPI LEP info
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} QPI_CPU_DATA;
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typedef struct {
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UINT8 Valid;
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UINT8 SocId;
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QPI_PEER_DATA PeerInfo[MAX_SOCKET]; // QPI LEP info
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} QPI_IIO_DATA;
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typedef struct {
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IIO_PORT_INFO PortInfo[NUMBER_PORTS_PER_SOCKET];
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} IIO_DMI_PCIE_INFO;
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typedef struct _STACK_RES {
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UINT8 Personality;
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UINT8 BusBase;
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UINT8 BusLimit;
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UINT16 PciResourceIoBase;
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UINT16 PciResourceIoLimit;
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UINT32 IoApicBase;
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UINT32 IoApicLimit;
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UINT32 Mmio32Base; // Base of low MMIO configured for this stack in memory map
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UINT32 Mmio32Limit; // Limit of low MMIO configured for this stack in memory map
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UINT64 Mmio64Base; // Base of high MMIO configured for this stack in memory map
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UINT64 Mmio64Limit; // Limit of high MMIO configured for this stack in memory map
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UINT32 PciResourceMem32Base; // Base of low MMIO resource available for PCI devices
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UINT32 PciResourceMem32Limit; // Limit of low MMIO resource available for PCI devices
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UINT64 PciResourceMem64Base; // Base of high MMIO resource available for PCI devices
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UINT64 PciResourceMem64Limit; // Limit of high MMIO resource available for PCI devices
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UINT32 VtdBarAddress;
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UINT32 Mmio32MinSize; // Minimum required size of MMIO32 resource needed for this stack
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} STACK_RES;
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typedef struct {
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UINT8 Valid;
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UINT8 SocketID; // Socket ID of the IIO (0..3)
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UINT8 BusBase;
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UINT8 BusLimit;
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UINT16 PciResourceIoBase;
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UINT16 PciResourceIoLimit;
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UINT32 IoApicBase;
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UINT32 IoApicLimit;
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UINT32 Mmio32Base; // Base of low MMIO configured for this socket in memory map
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UINT32 Mmio32Limit; // Limit of low MMIO configured for this socket in memory map
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UINT64 Mmio64Base; // Base of high MMIO configured for this socket in memory map
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UINT64 Mmio64Limit; // Limit of high MMIO configured for this socket in memory map
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STACK_RES StackRes[MAX_LOGIC_IIO_STACK];
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UINT32 RcBaseAddress;
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IIO_DMI_PCIE_INFO PcieInfo;
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UINT8 DmaDeviceCount;
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} IIO_RESOURCE_INSTANCE;
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typedef struct {
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UINT16 PlatGlobalIoBase; // Global IO Base
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UINT16 PlatGlobalIoLimit; // Global IO Limit
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UINT32 PlatGlobalMmio32Base; // Global Mmiol base
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UINT32 PlatGlobalMmio32Limit; // Global Mmiol limit
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UINT64 PlatGlobalMmio64Base; // Global Mmioh Base [43:0]
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UINT64 PlatGlobalMmio64Limit; // Global Mmioh Limit [43:0]
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QPI_CPU_DATA CpuQpiInfo[MAX_SOCKET]; // QPI related info per CPU
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QPI_IIO_DATA IioQpiInfo[MAX_SOCKET]; // QPI related info per IIO
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UINT32 MemTsegSize;
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UINT32 MemIedSize;
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UINT64 PciExpressBase;
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UINT32 PciExpressSize;
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UINT32 MemTolm;
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IIO_RESOURCE_INSTANCE IIO_resource[MAX_SOCKET];
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UINT8 numofIIO;
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UINT8 MaxBusNumber;
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UINT32 packageBspApicID[MAX_SOCKET]; // This data array is valid only for SBSP, not for non-SBSP CPUs. <AS> for CpuSv
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UINT8 EVMode;
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UINT8 Pci64BitResourceAllocation;
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UINT8 SkuPersonality[MAX_SOCKET];
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UINT8 VMDStackEnable[MaxIIO][MAX_IIO_STACK];
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UINT16 IoGranularity;
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UINT32 MmiolGranularity;
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UINT64_STRUCT MmiohGranularity;
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UINT8 RemoteRequestThreshold; //5370389
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UINT32 UboxMmioSize;
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UINT32 MaxAddressBits;
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} PLATFORM_DATA;
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typedef struct {
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UINT8 CurrentUpiiLinkSpeed;// Current programmed UPI Link speed (Slow/Full speed mode)
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UINT8 CurrentUpiLinkFrequency; // Current requested UPI Link frequency (in GT)
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UINT8 OutKtiCpuSktHotPlugEn; // 0 - Disabled, 1 - Enabled for PM X2APIC
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UINT32 OutKtiPerLinkL1En[MAX_SOCKET]; // output kti link enabled status for PM
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UINT8 IsocEnable;
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UINT32 meRequestedSize; // Size of the memory range requested by ME FW, in MB
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UINT32 ieRequestedSize; // Size of the memory range requested by IE FW, in MB
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UINT8 DmiVc1;
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UINT8 DmiVcm;
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UINT32 CpuPCPSInfo;
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UINT8 cpuSubType;
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UINT8 SystemRasType;
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UINT8 numCpus; // 1,..4. Total number of CPU packages installed and detected (1..4)by QPI RC
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UINT16 tolmLimit;
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UINT32 tohmLimit;
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RC_VERSION RcVersion;
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BOOLEAN MsrTraceEnable;
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UINT8 DdrXoverMode; // DDR 2.2 Mode
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// For RAS
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UINT8 bootMode;
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UINT8 OutClusterOnDieEn; // Whether RC enabled COD support
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UINT8 OutSncEn;
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UINT8 OutNumOfCluster;
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UINT8 imcEnabled[MAX_SOCKET][MAX_IMC];
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UINT16 LlcSizeReg;
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UINT8 chEnabled[MAX_SOCKET][MAX_CH];
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UINT8 memNode[MC_MAX_NODE];
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UINT8 IoDcMode;
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UINT8 ReservedBC;
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} SYSTEM_STATUS;
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typedef struct {
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PLATFORM_DATA PlatformData;
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SYSTEM_STATUS SystemStatus;
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UINT32 OemValue;
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} IIO_UDS;
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#pragma pack()
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#endif
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