/** @file
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This file provides required platform data structure for IOH.
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@copyright
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Copyright 1999 - 2021 Intel Corporation. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _IIO_PLATFORM_DATA_H_
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#define _IIO_PLATFORM_DATA_H_
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#include <Upi/KtiSi.h>
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#include <IioRegs.h>
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#include <IioConfig.h>
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typedef enum {
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DmiTypeVc0,
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DmiTypeVc1,
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DmiTypeVcm,
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MaxDmiVcType
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} DMI_VC_TYPE;
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typedef enum {
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DmiTypeTc0,
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DmiTypeTc1,
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DmiTypeTc2,
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DmiTypeTc3,
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DmiTypeTc4,
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DmiTypeTc5,
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DmiTypeTc6,
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DmiTypeTc7,
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MaxDmiTcType
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}DMI_TC_TYPE;
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#pragma pack(1)
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typedef union {
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struct {
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UINT32 Value;
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UINT32 ValueHigh;
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} Address32bit;
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UINT64 Address64bit;
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} IIO_PTR_ADDRESS;
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/*
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* Following are the data structure defined to support multiple CBDMA types on a system
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*/
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typedef struct {
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UINT32 NoSnoopSupported : 1;
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UINT32 RelaxOrderSupported : 1;
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} CB_CONFIG_CAPABILITY;
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typedef struct {
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UINT8 CB_VER;
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UINT8 BusNo;
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UINT8 DevNo;
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UINT8 FunNo;
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UINT8 MaxNoChannels;
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CB_CONFIG_CAPABILITY CBConfigCap;
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} CBDMA_CONTROLLER;
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typedef struct {
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CBDMA_CONTROLLER CbDmaDevice;
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} DMA_HOST;
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// <<<< end of CBDMA data structures >>>>
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typedef struct {
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UINT8 LinkWidth;
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UINT8 LinkSpeed;
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} IIO_DMI_DATA;
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typedef struct {
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UINT8 SystemRasType;
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BOOLEAN IsocEnable;
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UINT8 EVMode;
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UINT32 meRequestedSize;
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UINT32 ieRequestedSize;
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UINT8 DmiVc[MaxDmiVcType];
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UINT8 DmiVcId[MaxDmiVcType];
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UINT8 DmiTc[MaxDmiTcType];
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UINT8 PlatformType;
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UINT8 IOxAPICCallbackBootEvent;
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UINT8 RasOperation;
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UINT8 SocketUnderOnline;
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UINT8 CompletedReadyToBootEventServices;
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UINT8 SocketPresent[MaxIIO];
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UINT8 SocketBaseBusNumber[MaxIIO];
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UINT8 SocketLimitBusNumber[MaxIIO];
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UINT32 StackPresentBitmap[MaxIIO];
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UINT64_STRUCT SegMmcfgBase[MaxIIO];
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UINT8 SegmentSocket[MaxIIO];
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UINT8 SocketStackPersonality[MaxIIO][MAX_IIO_STACK];
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UINT8 SocketStackBus[MaxIIO][MAX_IIO_STACK];
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UINT8 SocketStackBaseBusNumber[MaxIIO][MAX_IIO_STACK];
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UINT8 SocketStackLimitBusNumber[MaxIIO][MAX_IIO_STACK];
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UINT32 SocketStackMmiolBase[MaxIIO][MAX_IIO_STACK];
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UINT32 SocketStackMmiolLimit[MaxIIO][MAX_IIO_STACK];
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UINT8 SocketPortBusNumber[MaxIIO][NUMBER_PORTS_PER_SOCKET];
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UINT8 StackPerPort[MaxIIO][NUMBER_PORTS_PER_SOCKET];
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UINT8 SocketUncoreBusNumber[MaxIIO][MAX_UNCORE_STACK]; // 10nm only
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UINT32 PchIoApicBase;
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UINT32 PciResourceMem32Base[MaxIIO];
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UINT32 PciResourceMem32Limit[MaxIIO];
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UINT8 Pci64BitResourceAllocation;
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UINT32 StackPciResourceMem32Limit[MaxIIO][MAX_IIO_STACK];
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UINT32 VtdBarAddress[MaxIIO][MAX_IIO_STACK];
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UINT32 IoApicBase[MaxIIO][MAX_IIO_STACK];
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UINT32 RcBaseAddress;
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UINT64 PciExpressBase;
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UINT32 PmBase[MaxIIO];
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UINT32 PchSegRegBaseAddress[MaxIIO];
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UINT8 PcieRiser1Type;
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UINT8 PcieRiser2Type;
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UINT8 DmiVc1;
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UINT8 DmiVcm;
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UINT8 Emulation;
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UINT8 SkuPersonality[MAX_SOCKET];
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UINT8 StackPersonality[MaxIIO][MAX_IIO_STACK];
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UINT8 StackId[MaxIIO][MAX_IIO_STACK];
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UINT8 VMDStackEnable[MaxIIO][MAX_IIO_STACK];
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UINT8 IODC;
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UINT8 MultiPch;
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UINT8 FpgaActive[MaxIIO];
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UINT32 TraceHubMemBase;
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UINT8 DmiSocketMap;
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IIO_DMI_DATA DmiSocketData[MAX_SOCKET];
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UINT64 PciTrainingStartTime; // time in microseconds
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} IIO_V_DATA;
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typedef struct {
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UINT8 Device;
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UINT8 Function;
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} IIO_PORT_INFO;
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typedef struct {
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UINT8 Valid;
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UINT8 IioUplinkPortIndex; //defines platform specific uplink port index (if any else FF)
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IIO_PORT_INFO UplinkPortInfo;
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} IIO_UPLINK_PORT_INFO;
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typedef struct _INTEL_IIO_PORT_INFO {
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UINT8 Device;
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UINT8 Function;
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UINT8 Reserved137;
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UINT8 Reserved138;
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UINT8 Reserved139;
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UINT8 Reserved140;
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UINT8 Reserved141;
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UINT8 SuperClusterPort;
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UINT8 NtbDevice;
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UINT8 NtbFunction;
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} INTEL_IIO_PORT_INFO;
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typedef struct _INTEL_DMI_PCIE_INFO {
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INTEL_IIO_PORT_INFO PortInfo[NUMBER_PORTS_PER_SOCKET];
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} INTEL_DMI_PCIE_INFO;
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typedef struct _INTEL_IIO_PRELINK_DATA {
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INTEL_DMI_PCIE_INFO PcieInfo;
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IIO_UPLINK_PORT_INFO UplinkInfo[MaxIIO];
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} INTEL_IIO_PRELINK_DATA;
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typedef struct {
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UINT8 PciePortPresent[MaxIIO*NUMBER_PORTS_PER_SOCKET];
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UINT8 PciePortConfig[MaxIIO*NUMBER_PORTS_PER_SOCKET];
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UINT8 PciePortOwnership[MaxIIO*NUMBER_PORTS_PER_SOCKET];
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UINT8 CurrentPXPMap[MaxIIO*NUMBER_PORTS_PER_SOCKET];
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UINT8 MaxPXPMap[MaxIIO * NUMBER_PORTS_PER_SOCKET]; // Max link width
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BOOLEAN LaneReversedPXPMap[MaxIIO][MAX_IOU_PER_SOCKET];
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UINT8 PciePortMaxWidth[MaxIIO*NUMBER_PORTS_PER_SOCKET];
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UINT8 PciePortNegWidth[MaxIIO*NUMBER_PORTS_PER_SOCKET];
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UINT8 PciePortNegSpeed[MaxIIO*NUMBER_PORTS_PER_SOCKET];
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UINT8 RetimerConnectCount[MaxIIO*NUMBER_PORTS_PER_SOCKET];
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IIO_PTR_ADDRESS PtrAddress;
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IIO_PTR_ADDRESS PtrPcieTopology;
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UINT64 McastRsvdMemory;
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DMA_HOST DMAhost[MaxIIO];
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UINT8 resetRequired;
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UINT8 MaxPciePortNumberPerSocket[MaxIIO];
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//
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// IsSocketSmbEnabled and TimeoutOnVppOccured are needed only as a WA for SMB issue in socket
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//
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BOOLEAN IsSocketSmbEnabled[MaxIIO]; // contains TRUE if socket smb controller was enabled for given IIO (socket)
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BOOLEAN TimeoutOnVppOccurred[MaxIIO]; // contains TRUE if there was a timeout after VPP programming
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} IIO_OUT_DATA;
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typedef struct {
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IIO_V_DATA IioVData;
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INTEL_IIO_PRELINK_DATA PreLinkData;
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IIO_OUT_DATA IioOutData;
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} IIO_VAR;
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typedef struct {
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IIO_CONFIG SetupData;
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IIO_VAR IioVar;
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} IIO_GLOBALS;
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#pragma pack()
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#endif //_IIO_PLATFORM_DATA_H_
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