/** @file
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Data format for Universal Data Structure
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@copyright
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Copyright 1999 - 2021 Intel Corporation. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef __SOCKET_PROCESSORCORE_CONFIGURATION_DATA_H__
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#define __SOCKET_PROCESSORCORE_CONFIGURATION_DATA_H__
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#include <UncoreCommonIncludes.h>
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extern EFI_GUID gEfiSocketProcessorCoreVarGuid;
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#define SOCKET_PROCESSORCORE_CONFIGURATION_NAME L"SocketProcessorCoreConfig"
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#pragma pack(1)
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typedef struct {
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UINT8 CpuidMaxValue;
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UINT8 ProcessorHyperThreadingDisable; // Hyper Threading [ALL]
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UINT8 ProcessorVmxEnable; // Enabling VMX
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UINT8 ProcessorSmxEnable; // Enabling SMX (TXT LT)
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UINT8 ProcessorLtsxEnable; // Enabling TXT (TXT LT-SX)
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UINT8 ThreeStrikeTimer; // Disable 3strike timer
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UINT8 FastStringEnable; // Fast String
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UINT8 MachineCheckEnable; // Machine Check
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UINT8 MlcStreamerPrefetcherEnable; // Hardware Prefetch
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UINT8 MlcSpatialPrefetcherEnable; // Adjacent Cache Line Prefetch
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UINT8 DCUStreamerPrefetcherEnable; // DCU Streamer Prefetcher
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UINT8 DCUIPPrefetcherEnable; // DCU IP Prefetcher
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UINT8 DCUModeSelection; // DCU Mode Selection
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UINT8 ProcessorX2apic; // Enable Processor XAPIC
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UINT8 BspSelection; // Select BSP
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UINT8 IedTraceSize; // IED trace size
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UINT8 TsegSize; // TSEG size
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UINT8 AllowMixedPowerOnCpuRatio; // Allow Mixed PowerOn CpuRatio
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UINT8 CheckCpuBist; // check and disable BIST faile core or ignore
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UINT8 CoreFailover; // Enable spare core(s) in place of core(s) that fail BIST
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UINT64 ReservedS192;
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UINT8 ProcessorFlexibleRatio; // Non-Turbo Mode Processor Core Ratio Multiplier
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UINT8 ProcessorFlexibleRatioOverrideEnable; // Non-Turbo Mode Processor Core Ratio Multiplier Enable
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UINT8 ForcePhysicalModeEnable; // Force physical destionation mode
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UINT8 LlcPrefetchEnable; // LLC Prefetch
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UINT8 CpuMtoIWa; // MtoI Workaround;
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UINT8 ProcessorVirtualWireMode;
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UINT8 ProcessorMsrLockControl; // MSR Lock Bit Control
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UINT8 ProcessorMsrPkgCstConfigControlLock; // MSR PKG_CST_CONFIG_CONTROL lock
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UINT8 DebugInterface; // IA32_DEBUG_INTERFACE_MSR
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UINT8 AesEnable;
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UINT8 PpinControl; // PPIN Control MSR
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UINT8 LockChipset; // Lock Chipset
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UINT8 BiosAcmErrorReset; // Disable LT-SX and reset system when BIOS ACM error occurs
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UINT8 AcmType; // 0x80 = debug signed ACM; 0x40 = NPW production signed ACM; 0x00 = PW production signed ACM
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// SecurityPolicy Stalagmite
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#include <Guid/SecurityPolicy_Flat.h>
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UINT8 SkipStopPbet; // Skip StopPbet
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UINT64 CoreDisableMask[MAX_SOCKET]; // one for each CPU socket
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// IOT/OCLA configs
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#ifndef OCLA_TOR_ENTRY_MAX
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#define OCLA_TOR_ENTRY_MIN 0
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#define OCLA_TOR_ENTRY_MAX 0x11 // 15 or 17 depending on Isoch on/off
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#define OCLA_TOR_ENTRY_DEFAULT 1
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#define OCLA_WAY_MIN 0
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#define OCLA_WAY_MAX 8 // max 8 LLC ways out of 11 can be reserved for OCLA
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#define OCLA_WAY_DEFAULT 1
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#endif
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UINT8 IotEn[MAX_SOCKET];
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UINT8 OclaMaxTorEntry[MAX_SOCKET];
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UINT8 OclaMinWay[MAX_SOCKET];
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UINT32 IioLlcWaysMask; // MSR CBO_SLICE0_CR_IIO_LLC_WAYS bitmask.
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UINT32 ExpandedIioLlcWaysMask; // MSR INGRESS_SPARE[10:0] bitmask. - Only Bits[10:0] are used
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UINT32 RemoteWaysMask; // MSR INGRESS_SPARE[26:16] bitmask. - Only Bits[10:0] are used
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UINT8 PCIeDownStreamPECIWrite;
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//
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// SMM Blocked and SMM Delayed
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//
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UINT8 SmmBlockedDelayed;
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//
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// eSMM Save State Mode
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//
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UINT8 eSmmSaveState;
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UINT8 PeciInTrustControlBit; //On Setup
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UINT8 PeciAgtLegacyTrustBit;
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UINT8 PeciAgtSmbusTrustBit;
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UINT8 PeciAgtIeTrustBit;
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UINT8 PeciAgtGenericTrustBit;
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UINT8 PeciAgtEspiTrustBit;
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UINT8 Poison;
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UINT8 Viral;
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UINT8 EVMode;
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UINT8 SmbusErrorRecovery;
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UINT8 CpuL1NextPagePrefetcherDisable;
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UINT8 CpuPaLimit;
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UINT8 RdtCatOpportunisticTuning;
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UINT8 CpuDbpEnable; // Enable/Disable DBP-F
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UINT8 GlobalPsmiEnable;
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UINT8 PsmiTrace[MAX_SOCKET];
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UINT8 PsmiHandlerSize[MAX_SOCKET];
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UINT8 PsmiTraceRegion0[MAX_SOCKET];
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UINT8 PsmiTraceBufferSizeRegion0[MAX_SOCKET];
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UINT8 PsmiTraceMemTypeRegion0[MAX_SOCKET];
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UINT8 PsmiTraceRegion1[MAX_SOCKET];
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UINT8 PsmiTraceBufferSizeRegion1[MAX_SOCKET];
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UINT8 PsmiTraceMemTypeRegion1[MAX_SOCKET];
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UINT8 PsmiTraceRegion2[MAX_SOCKET];
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UINT8 PsmiTraceBufferSizeRegion2[MAX_SOCKET];
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UINT8 PsmiTraceMemTypeRegion2[MAX_SOCKET];
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UINT8 PsmiTraceRegion3[MAX_SOCKET];
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UINT8 PsmiTraceBufferSizeRegion3[MAX_SOCKET];
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UINT8 PsmiTraceMemTypeRegion3[MAX_SOCKET];
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UINT8 PsmiTraceRegion4[MAX_SOCKET];
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UINT8 PsmiTraceBufferSizeRegion4[MAX_SOCKET];
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UINT8 PsmiTraceMemTypeRegion4[MAX_SOCKET];
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UINT8 L2RfoPrefetchDisable; // L2 RFO Prefetch
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UINT8 AmpPrefetchEnable;
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UINT8 TscResetEnable;
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UINT8 AcExceptionOnSplitLockEnable;
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// FuSa (SAF) Start
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UINT8 SafSupport;
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UINT8 EnableSaf;
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// FuSa (SAF) End
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UINT8 CFRS3mEnable;
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UINT8 CFRS3mManualCommit;
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UINT8 CFRPucodeEnable;
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UINT8 CFRPucodeManualCommit;
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UINT8 CpuCrashLogGprs;
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} SOCKET_PROCESSORCORE_CONFIGURATION;
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#pragma pack()
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#endif
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