/** @file
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Data format for Universal Data Structure
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@copyright
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Copyright 1999 - 2021 Intel Corporation. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _SOCKET_IIO_VARIABLE_H_
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#define _SOCKET_IIO_VARIABLE_H_
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#include <UncoreCommonIncludes.h>
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extern EFI_GUID gEfiSocketIioVariableGuid;
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#define SOCKET_IIO_CONFIGURATION_NAME L"SocketIioConfig"
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/*
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These vars are not used anywhere - it is left here for reference as this is used in comments below.
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Number must be used directly because of VFR compiler...
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#ifndef MAX_STACKS_PER_SOCKET_VAR
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#define MAX_STACKS_PER_SOCKET_VAR 6
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#define MAX_PORTS_PER_SOCKET_VAR 21
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#endif
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#endif
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*/
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#if MAX_SOCKET == 1
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#define TOTAL_VMD_STACKS_VAR 6 // MAX_STACKS_PER_SOCKET_VAR * MAX_SOCKET
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#define TOTAL_NTB_PORTS_VAR 5 // NUMBER_NTB_PORTS_PER_SOCKET * MAX_SOCKET
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#define TOTAL_IOU_VAR 5 // MAX_IOU_PER_SOCKET * MAX_SOCKET
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#define TOTAL_VMD_PCH_ROOTPORTS_VAR 20 // MAX_PCH_ROOTPORTS * MAX_SOCKET
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#define TOTAL_RETIMERS_VAR 12 // MAX_SOCKET * MAX_STACKS_PER_SOCKET_VAR * MAX_RETIMERS_PER_STACK (ICX-SP related)
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#define TOTAL_NPK_VAR 1 // NUMBER_TRACE_HUB_PER_SOCKET * MAX_SOCKET
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#define TOTAL_PORTS_VAR 21 // MAX_PORTS_PER_SOCKET_VAR * MAX_SOCKET
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#define TOTAL_VMD_PORTS_VAR 24 // MAX_PORTS_PER_STACK * MAX_STACKS_PER_SOCKET_VAR * MAX_SOCKET
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#define TOTAL_DSA_VAR 1 // 1_DSA_PER_SOCKET * MAX_SOCKET
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#define TOTAL_IAX_VAR 1 // 1_IAX_PER_SOCKET * MAX_SOCKET
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#define TOTAL_CPM_VAR 1 // 1_CPM_PER_SOCKET * MAX_SOCKET
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#define TOTAL_HQM_VAR 1 // 1_HQM_PER_SOCKET * MAX_SOCKET
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#endif
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#if MAX_SOCKET == 4
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#define TOTAL_VMD_STACKS_VAR 24 // MAX_STACKS_PER_SOCKET_VAR * MAX_SOCKET
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#define TOTAL_NTB_PORTS_VAR 20 // NUMBER_NTB_PORTS_PER_SOCKET * MAX_SOCKET
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#define TOTAL_IOU_VAR 20 // MAX_IOU_PER_SOCKET * MAX_SOCKET
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#define TOTAL_VMD_PCH_ROOTPORTS_VAR 80 // MAX_PCH_ROOTPORTS * MAX_SOCKET
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#define TOTAL_RETIMERS_VAR 48 // MAX_SOCKET * MAX_STACKS_PER_SOCKET_VAR * MAX_RETIMERS_PER_STACK (ICX-SP related)
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#define TOTAL_NPK_VAR 4 // NUMBER_TRACE_HUB_PER_SOCKET * MAX_SOCKET
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#define TOTAL_PORTS_VAR 84 // MAX_PORTS_PER_SOCKET_VAR * MAX_SOCKET
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#define TOTAL_VMD_PORTS_VAR 96 // MAX_PORTS_PER_STACK * MAX_STACKS_PER_SOCKET_VAR * MAX_SOCKET
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#define TOTAL_DSA_VAR 4 // 1_DSA_PER_SOCKET * MAX_SOCKET
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#define TOTAL_IAX_VAR 4 // 1_IAX_PER_SOCKET * MAX_SOCKET
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#define TOTAL_CPM_VAR 4 // 1_CPM_PER_SOCKET * MAX_SOCKET
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#define TOTAL_HQM_VAR 4 // 1_HQM_PER_SOCKET * MAX_SOCKET
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#endif
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#if MAX_SOCKET == 2
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#define TOTAL_VMD_STACKS_VAR 12 // MAX_STACKS_PER_SOCKET_VAR * MAX_SOCKET
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#define TOTAL_NTB_PORTS_VAR 10 // NUMBER_NTB_PORTS_PER_SOCKET * MAX_SOCKET
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#define TOTAL_IOU_VAR 10 // MAX_IOU_PER_SOCKET * MAX_SOCKET
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#define TOTAL_VMD_PCH_ROOTPORTS_VAR 40 // MAX_PCH_ROOTPORTS * MAX_SOCKET
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#define TOTAL_RETIMERS_VAR 24 // MAX_SOCKET * MAX_STACKS_PER_SOCKET_VAR * MAX_RETIMERS_PER_STACK (ICX-SP related)
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#define TOTAL_NPK_VAR 2 // NUMBER_TRACE_HUB_PER_SOCKET * MAX_SOCKET
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#define TOTAL_PORTS_VAR 42 // MAX_PORTS_PER_SOCKET_VAR * MAX_SOCKET
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#define TOTAL_VMD_PORTS_VAR 48 // MAX_PORTS_PER_STACK * MAX_STACKS_PER_SOCKET_VAR * MAX_SOCKET
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#define TOTAL_DSA_VAR 2 // 1_DSA_PER_SOCKET * MAX_SOCKET
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#define TOTAL_IAX_VAR 2 // 1_IAX_PER_SOCKET * MAX_SOCKET
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#define TOTAL_CPM_VAR 2 // 1_CPM_PER_SOCKET * MAX_SOCKET
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#define TOTAL_HQM_VAR 2 // 1_HQM_PER_SOCKET * MAX_SOCKET
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#endif
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#if MAX_SOCKET > 4
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#define TOTAL_VMD_PCH_ROOTPORTS_VAR 160 // MAX_PCH_ROOTPORTS * MAX_SOCKET
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#define TOTAL_NTB_PORTS_VAR 40 // NUMBER_NTB_PORTS_PER_SOCKET * MAX_SOCKET
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#define TOTAL_IOU_VAR 40 // MAX_IOU_PER_SOCKET * MAX_SOCKET
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#define TOTAL_VMD_STACKS_VAR 48 // MAX_STACKS_PER_SOCKET_VAR * MAX_SOCKET
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#define TOTAL_RETIMERS_VAR 96 // MAX_SOCKET * MAX_STACKS_PER_SOCKET_VAR * MAX_RETIMERS_PER_STACK (ICX-SP related)
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#define TOTAL_NPK_VAR 8 // NUMBER_TRACE_HUB_PER_SOCKET * MAX_SOCKET
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#define TOTAL_PORTS_VAR 168 // MAX_PORTS_PER_SOCKET_VAR * MAX_SOCKET
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#define TOTAL_VMD_PORTS_VAR 192 // MAX_PORTS_PER_STACK * MAX_STACKS_PER_SOCKET_VAR * MAX_SOCKET
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#define TOTAL_DSA_VAR MAX_SOCKET // 1_DSA_PER_SOCKET * MAX_SOCKET
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#define TOTAL_IAX_VAR MAX_SOCKET // 1_IAX_PER_SOCKET * MAX_SOCKET
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#define TOTAL_CPM_VAR MAX_SOCKET // 1_CPM_PER_SOCKET * MAX_SOCKET
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#define TOTAL_HQM_VAR MAX_SOCKET // 1_HQM_PER_SOCKET * MAX_SOCKET
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#endif
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#pragma pack(1)
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typedef struct {
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/**
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==================================================================================================
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================================== VTd Setup Options ==================================
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==================================================================================================
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**/
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UINT8 VTdSupport;
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UINT8 DmaCtrlOptIn;
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UINT8 InterruptRemap;
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UINT8 PostedInterrupt;
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UINT8 ATS;
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UINT8 CoherencySupport;
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/**
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==================================================================================================
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================================== PCIE Setup Options ==================================
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==================================================================================================
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**/
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// Vars used to configure (disable/greyout) parts of setup menu
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UINT8 IioPresent[MAX_SOCKET];
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UINT8 IioStackPresent[TOTAL_IIO_STACKS]; // based on sysInfo data
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UINT8 PchPresentOnStack[MAX_SOCKET]; // stub for multiPCH
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UINT8 RetimerPresent[TOTAL_RETIMERS_VAR]; // retimer detected in stack
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UINT8 VtdAcsWa;
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// Platform data needs to update these PCI Configuration settings
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UINT8 PcieHotPlugOnPort[TOTAL_PORTS_VAR];
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UINT8 SLOTHPSUP[TOTAL_PORTS_VAR]; // Hot Plug surprise supported - Slot Capabilities (D0-10 / F0 / R0xA4 / B5)
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// General PCIE Configuration
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UINT8 ConfigIOU0[MAX_SOCKET];
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UINT8 ConfigIOU1[MAX_SOCKET];
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UINT8 ConfigIOU2[MAX_SOCKET];
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UINT8 ConfigIOU3[MAX_SOCKET];
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UINT8 ConfigIOU4[MAX_SOCKET];
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UINT8 ConfigIOU5[MAX_SOCKET];
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UINT8 ConfigIOU6[MAX_SOCKET];
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UINT8 ConfigIOU7[MAX_SOCKET];
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UINT8 PcieSubSystemMode[TOTAL_IOU_VAR];
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UINT8 CompletionTimeoutGlobal;
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UINT8 CompletionTimeoutGlobalValue;
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UINT8 CompletionTimeout[MAX_SOCKET]; // On Setup
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UINT8 CompletionTimeoutValue[MAX_SOCKET]; // On Setup
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UINT8 CoherentReadPart;
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UINT8 CoherentReadFull;
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UINT8 PcieGlobalAspm;
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UINT8 StopAndScream;
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UINT8 SnoopResponseHoldOff;
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//
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// PCIE capability
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//
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UINT8 PCIe_LTR;
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UINT8 PcieExtendedTagField;
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UINT8 Pcie10bitTag;
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UINT8 PCIe_AtomicOpReq;
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UINT8 PcieMaxReadRequestSize;
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UINT8 PciePtm;
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UINT8 RpCorrectableErrorEsc[MAX_SOCKET]; //on Setup
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UINT8 RpUncorrectableNonFatalErrorEsc[MAX_SOCKET]; //on Setup
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UINT8 RpUncorrectableFatalErrorEsc[MAX_SOCKET]; //on Setup
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// mixc PCIE configuration
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UINT8 PcieLinkDis[TOTAL_PORTS_VAR]; // On Setup
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UINT8 PcieAspm[TOTAL_PORTS_VAR]; // On Setup
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UINT8 PcieCommonClock[TOTAL_PORTS_VAR]; // On Setup
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UINT8 PcieMaxPayload[TOTAL_PORTS_VAR]; // On Setup PRD
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UINT8 PcieDState[TOTAL_PORTS_VAR]; // On Setup
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UINT8 PcieL1Latency[TOTAL_PORTS_VAR]; // On Setup
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UINT8 MsiEn[TOTAL_PORTS_VAR]; // On Setup
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UINT8 ExtendedSync[TOTAL_PORTS_VAR]; // On Setup
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UINT8 PciePortEnable[TOTAL_PORTS_VAR]; // On Setup
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UINT8 IODC[TOTAL_PORTS_VAR]; // On Setup
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UINT8 MctpEn[TOTAL_PORTS_VAR]; // On Setup
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//
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// PCIE setup options for Link Control2
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//
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UINT8 PciePortLinkSpeed[TOTAL_PORTS_VAR]; //on Setup
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UINT8 ComplianceMode[TOTAL_PORTS_VAR]; // On Setup PRD
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UINT8 PciePortLinkMaxWidth[TOTAL_PORTS_VAR]; // On Setup
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UINT8 DeEmphasis[TOTAL_PORTS_VAR]; // On Setup
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//
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// PCIE setup options for MISCCTRLSTS
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//
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UINT8 EOI[TOTAL_PORTS_VAR]; // On Setup
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UINT8 MSIFATEN[TOTAL_PORTS_VAR]; //On Setup.
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UINT8 MSINFATEN[TOTAL_PORTS_VAR]; //On Setup.
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UINT8 MSICOREN[TOTAL_PORTS_VAR]; //On Setup.
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UINT8 ACPIPMEn[TOTAL_PORTS_VAR]; //On Setup
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UINT8 P2PRdDis[TOTAL_PORTS_VAR]; //On Setup Peer 2 peer
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UINT8 DisPMETOAck[TOTAL_PORTS_VAR]; //On Setup
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UINT8 ACPIHP[TOTAL_PORTS_VAR]; //On Setup
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UINT8 ACPIPM[TOTAL_PORTS_VAR]; //On Setup
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UINT8 SRIS[TOTAL_PORTS_VAR]; //On Setup
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UINT8 TXEQ[TOTAL_PORTS_VAR]; //On Setup
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UINT8 SERRE[TOTAL_PORTS_VAR]; //On Setup
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//
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// PCIE RAS (Errors)
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//
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UINT8 PcieUnsupportedRequests[TOTAL_PORTS_VAR]; // Unsupported Request per-port option
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//
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// PCIE Link Training Ctrl
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//
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//
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// North Peak (NPK)
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//
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UINT8 NorthTraceHubMode[TOTAL_NPK_VAR];
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UINT32 NorthTraceHubMemReg0Size[TOTAL_NPK_VAR];
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UINT32 NorthTraceHubMemReg1Size[TOTAL_NPK_VAR];
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//
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// Sierra Peak (SPK)
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//
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UINT8 SierraPeakMemBufferSize[MAX_SOCKET];
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//
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// MMIO poison enabling per stack
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//
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UINT8 PoisonMmioReadEn[TOTAL_IIO_STACKS]; // on setup
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/**
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==================================================================================================
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================================== Crystal Beach 3 Setup Options ===========================
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==================================================================================================
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**/
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UINT8 Cb3DmaEn[TOTAL_CB3_DEVICES]; // on setup
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UINT8 Cb3NoSnoopEn[TOTAL_CB3_DEVICES]; // on setup
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UINT8 DisableTPH;
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UINT8 PrioritizeTPH;
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UINT8 CbRelaxedOrdering;
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UINT8 CbDmaMultiCastEnable; // CbDmaMultiCastEnable test enable
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UINT8 DsaEn[TOTAL_DSA_VAR]; // on setup
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UINT8 IaxEn[TOTAL_IAX_VAR]; // on setup
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UINT8 CpmEn[TOTAL_CPM_VAR]; // on setup
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UINT8 HqmEn[TOTAL_HQM_VAR]; // on setup
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/**
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==================================================================================================
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================================== MISC IOH Setup Options ==========================
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==================================================================================================
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**/
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// The following are for hiding each individual device and function
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UINT8 PEXPHIDE[TOTAL_PORTS_VAR]; // Hide any of the DMI or PCIE devices - SKT 0,1,2,3; Device 0-10 PRD
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UINT8 DevPresIoApicIio[TOTAL_IIO_STACKS];
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// Hide IOAPIC Device 5, Function 4
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UINT8 PCUF6Hide; // Hide Device PCU Device 30, Function 6
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UINT8 EN1K; // Enable/Disable 1K granularity of IO for P2P bridges 0:20:0:98 bit 2
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UINT8 DualCvIoFlow; // Dual CV IO Flow
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UINT8 Xppdef;
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UINT8 Pci64BitResourceAllocation;
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UINT8 PcieBiosTrainEnable; // Used as a work around for A0 PCIe
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UINT8 MultiCastEnable; // MultiCastEnable test enable
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UINT8 McastBaseAddrRegion; // McastBaseAddrRegion
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UINT8 McastIndexPosition; // McastIndexPosition
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UINT8 McastNumGroup; // McastNumGroup
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UINT8 HidePEXPMenu[TOTAL_PORTS_VAR]; // to suppress /display the PCIe port menu
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/**
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==================================================================================================
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================================== NTB Related Setup Options ==========================
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==================================================================================================
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**/
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UINT8 NtbPpd[TOTAL_NTB_PORTS_VAR]; //on setup option
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UINT8 NtbBarSizeOverride[TOTAL_NTB_PORTS_VAR]; //on setup option
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UINT8 NtbSplitBar[TOTAL_NTB_PORTS_VAR]; //on setup option
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UINT8 NtbBarSizeImBar1[TOTAL_NTB_PORTS_VAR]; //on setup option
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UINT8 NtbBarSizeImBar2[TOTAL_NTB_PORTS_VAR]; //on setup option
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UINT8 NtbBarSizeImBar2_0[TOTAL_NTB_PORTS_VAR]; //on setup option
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UINT8 NtbBarSizeImBar2_1[TOTAL_NTB_PORTS_VAR]; //on setup option
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UINT8 NtbBarSizeEmBarSZ1[TOTAL_NTB_PORTS_VAR]; //on setup option
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UINT8 NtbBarSizeEmBarSZ2[TOTAL_NTB_PORTS_VAR]; //on setup option
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UINT8 NtbBarSizeEmBarSZ2_0[TOTAL_NTB_PORTS_VAR]; //on setup option
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UINT8 NtbBarSizeEmBarSZ2_1[TOTAL_NTB_PORTS_VAR]; //on setup option
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UINT8 NtbXlinkCtlOverride[TOTAL_NTB_PORTS_VAR]; //on setup option
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UINT8 NtbLinkBiosTrainEn;
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/**
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==================================================================================================
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================================== VMD Related Setup Options ==========================
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==================================================================================================
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**/
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UINT8 VMDEnabled[TOTAL_VMD_STACKS_VAR]; // indicates if VMD is enabled on given stack
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UINT8 VMDPortEnable[TOTAL_VMD_PORTS_VAR]; // indicated if VMD is enabled on given port is enabled
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UINT8 VMDPchPortAllowed[TOTAL_VMD_PCH_ROOTPORTS_VAR]; // indicates if VMD CAN BE enabled on given PCH Rp
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UINT8 VMDPchPortEnable[TOTAL_VMD_PCH_ROOTPORTS_VAR]; // indicates if VMD IS enabled on given PCH Rp
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UINT8 VMDHotPlugEnable[TOTAL_VMD_STACKS_VAR];
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UINT8 VMDCfgBarSz[TOTAL_VMD_STACKS_VAR];
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UINT8 VMDCfgBarAttr[TOTAL_VMD_STACKS_VAR];
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UINT8 VMDMemBarSz1[TOTAL_VMD_STACKS_VAR];
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UINT8 VMDMemBar1Attr[TOTAL_VMD_STACKS_VAR];
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UINT8 VMDMemBarSz2[TOTAL_VMD_STACKS_VAR];
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UINT8 VMDMemBar2Attr[TOTAL_VMD_STACKS_VAR];
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UINT8 VMDDirectAssign[TOTAL_VMD_STACKS_VAR];
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/**
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==================================================================================================
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================================== PCIe SSD Related Setup Options ==========================
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==================================================================================================
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**/
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UINT8 PcieAICEnabled[TOTAL_VMD_STACKS_VAR];
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UINT8 PcieAICPortEnable[TOTAL_PORTS_VAR];
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UINT8 PcieAICHotPlugEnable[TOTAL_VMD_STACKS_VAR];
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/**
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==================================================================================================
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================================== Retimers Related Setup Options ==========================
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==================================================================================================
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**/
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UINT32 RetimerGlParmReg0Override[TOTAL_RETIMERS_VAR];
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UINT32 RetimerPseudoPort0Reg2Override[TOTAL_RETIMERS_VAR];
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UINT32 RetimerPseudoPort1Reg2Override[TOTAL_RETIMERS_VAR];
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/**
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==================================================================================================
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======================== PCI-E Port Clock Gating Related Setup Options ========================
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==================================================================================================
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**/
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UINT8 PciePortClkGateEnable[TOTAL_PORTS_VAR]; // Indicates Clock gating for this PCIe port is enabled or not
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/**
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==================================================================================================
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================================== PCIe Global Related Setup Options ==========================
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==================================================================================================
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**/
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UINT8 NoSnoopRdCfg; //on Setup
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UINT8 NoSnoopWrCfg; //on Setup
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UINT8 MaxReadCompCombSize; //on Setup
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UINT8 ProblematicPort; //on Setup
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UINT8 DmiAllocatingFlow; //on Setup
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UINT8 PcieAllocatingFlow; //on Setup
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UINT8 PcieHotPlugEnable; //on Setup
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UINT8 PcieAcpiHotPlugEnable; //on Setup
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UINT8 PcieLowLatencyRetimersEnabled;
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UINT8 HaltOnDmiDegraded; //on Setup
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UINT8 RxClockWA;
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UINT8 GlobalPme2AckTOCtrl; //on Setup
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UINT8 PcieSlotOprom1; //On Setup
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UINT8 PcieSlotOprom2; //On Setup
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UINT8 PcieSlotOprom3; //On Setup
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UINT8 PcieSlotOprom4; //On Setup
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UINT8 PcieSlotOprom5; //On Setup
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UINT8 PcieSlotOprom6; //On Setup
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UINT8 PcieSlotOprom7; //On Setup
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UINT8 PcieSlotOprom8; //On Setup
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UINT8 PcieSlotItemCtrl; //On Setup
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UINT8 PcieRelaxedOrdering; //On Setup
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UINT8 PciePhyTestMode; //On setup
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UINT8 PcieEnqCmdSupport; //On setup
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UINT16 DelayBeforePCIeLinkTraining; //On Setup
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/**
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==================================================================================================
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================================== Reserved Setup Options ==========================
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==================================================================================================
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**/
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UINT8 ReservedS9;
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UINT8 ReservedS10;
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UINT8 ReservedS11; // On Setup
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UINT8 ReservedS12; // On Setup
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UINT8 ReservedS13; // On Setup
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UINT8 ReservedS14; // On Setup
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UINT8 ReservedS15; // On Setup
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UINT8 ReservedS16; // On Setup
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UINT8 ReservedS17; // On Setup
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UINT8 ReservedS18; // On Setup
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UINT8 ReservedS19; // On Setup
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UINT8 ReservedS20; // On Setup
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UINT32 ReservedS21[MAX_DEVHIDE_REGS_PER_SYSTEM]; // On Setup
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UINT8 ReservedS22[TOTAL_PORTS_VAR]; // On Setup
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UINT8 ReservedS23[TOTAL_PORTS_VAR]; //On Setup
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UINT8 ReservedS24[TOTAL_PORTS_VAR]; //On Setup
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UINT8 ReservedS25[TOTAL_PORTS_VAR]; //On Setup
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UINT8 ReservedS26[TOTAL_PORTS_VAR]; //On Setup
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UINT8 ReservedS27[TOTAL_PORTS_VAR]; //On Setup
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UINT8 ReservedS28[TOTAL_PORTS_VAR]; //On Setup
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UINT8 ReservedS29[TOTAL_PORTS_VAR]; //On Setup
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UINT8 ReservedS30[TOTAL_PORTS_VAR]; //On Setup
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UINT8 ReservedS31[TOTAL_PORTS_VAR]; //On Setup
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UINT8 ReservedS32[TOTAL_PORTS_VAR]; //On Setup
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UINT8 ReservedS33[TOTAL_PORTS_VAR]; //On Setup
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UINT8 ReservedS34[TOTAL_PORTS_VAR]; //On Setup
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UINT8 ReservedS35[TOTAL_PORTS_VAR]; //On Setup
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UINT8 ReservedS36[TOTAL_PORTS_VAR]; //On Setup
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UINT8 ReservedS37[TOTAL_PORTS_VAR]; //On Setup
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UINT8 ReservedS38[TOTAL_PORTS_VAR]; //On Setup
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UINT8 ReservedS39[TOTAL_PORTS_VAR]; //On Setup
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UINT8 ReservedS40[TOTAL_PORTS_VAR]; //On Setup
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UINT8 ReservedS41[TOTAL_PORTS_VAR]; //On Setup
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UINT8 ReservedS42[TOTAL_PORTS_VAR]; //On Setup
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UINT8 ReservedS43[TOTAL_PORTS_VAR]; //On Setup
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UINT8 ReservedS44[TOTAL_PORTS_VAR];
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UINT8 ReservedS45[TOTAL_PORTS_VAR]; //On Setup
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UINT8 ReservedS46; //On Setup
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UINT8 ReservedS47; //On Setup
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/**
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==================================================================================================
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====================== IIO Global Performance Tuner Related Setup Options =====================
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==================================================================================================
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**/
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UINT8 PerformanceTuningMode;
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/**
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==================================================================================================
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====================== PCI-E Data Link Feature Exchange Enable ===============================
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==================================================================================================
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**/
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UINT8 PcieDataLinkFeatureExchangeEnable[TOTAL_PORTS_VAR]; //On Setup
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/**
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==================================================================================================
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====================== Variables added post Beta ===============================
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==================================================================================================
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**/
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UINT8 PcieTxRxDetPoll[TOTAL_PORTS_VAR];
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UINT8 EcrcGenEn[TOTAL_PORTS_VAR]; //On Setup
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UINT8 EcrcChkEn[TOTAL_PORTS_VAR]; //On Setup
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UINT8 ControlIommu;
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UINT32 VtdDisabledBitmask[MAX_SOCKET];
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UINT8 X2ApicOptOut;
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UINT8 SkipRetimersDetection;
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UINT8 VtdPciAcsCtlWaEn; // Enables override of ACSCTL on PCIe root ports for VTd
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UINT8 VtdPciAcsCtlBit0;
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UINT8 VtdPciAcsCtlBit1;
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UINT8 VtdPciAcsCtlBit2;
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UINT8 VtdPciAcsCtlBit3;
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UINT8 VtdPciAcsCtlBit4;
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UINT8 AltAttenTable[TOTAL_PORTS_VAR]; //On Setup
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} SOCKET_IIO_CONFIGURATION;
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#pragma pack()
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#endif // _SOCKET_IIO_VARIABLE_H_
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