/** @file
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@copyright
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Copyright 1999 - 2021 Intel Corporation. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _PLATFORM_INFO_H_
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#define _PLATFORM_INFO_H_
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#include <PlatformInfoTypes.h>
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extern EFI_GUID gEfiPlatformInfoGuid;
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#pragma pack(1)
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typedef struct {
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UINT32 ReservedPci;
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} EFI_PLATFORM_PCI_DATA;
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typedef struct {
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UINT32 ReservedCpu;
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} EFI_PLATFORM_CPU_DATA;
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typedef struct {
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UINT64 SysIoApicEnable;
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UINT8 SysSioExist;
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UINT8 IsocEn; // Isoc Enabled
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UINT8 MeSegEn; // Me Seg Enabled.
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UINT8 DmiVc1; // 0 - Disable, 1 - Enable
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UINT8 SocketConfig;
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UINT8 DmiVcm; // 0 - Disable, 1 - Enable
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UINT8 DmiReserved; // for alignment
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} EFI_PLATFORM_SYS_DATA;
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typedef struct {
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UINT32 BiosGuardPhysBase;
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UINT32 BiosGuardMemSize;
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UINT32 MemTsegSize;
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UINT32 MemIedSize;
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#ifdef LT_FLAG
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UINT32 MemLtMemSize; // Below TSEG, contains (high to low: (Heap, SinitMem, reserved)3M, LtDevMemNonDMA 2M)
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UINT32 MemDprMemSize; // 6M DPR contained in LtMem
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UINT32 MemLtMemAddress;
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#endif // #ifdef LT_FLAG
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UINT64 PsmiUcTraceRegionBase;
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UINT64 PsmiUcTraceRegionSize;
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} EFI_PLATFORM_MEM_DATA;
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typedef struct {
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UINT8 PchPciePortCfg1; // PCIE Port Configuration Strap 1
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UINT8 PchPciePortCfg2; // PCIE Port Configuration Strap 2
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UINT8 PchPciePortCfg3; // PCIE Port Configuration Strap 3
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UINT8 PchPciePortCfg4; // PCIE Port Configuration Strap 4
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UINT8 PchPciePortCfg5; // PCIE Port Configuration Strap 5
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UINT8 PchPcieSBDE;
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UINT8 LomLanSupported; // Indicates if PCH LAN on board is supported or not
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UINT8 GbePciePortNum; // Indicates the PCIe port qhen PCH LAN on board is connnected.
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UINT8 GbeRegionInvalid;
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BOOLEAN GbeEnabled; // Indicates if the GBE is SS disabled
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UINT8 PchStepping;
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} EFI_PLATFORM_PCH_DATA;
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//
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// Platform Deep Sleep Feature
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//
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typedef struct {
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UINT8 PlatformDeepS5;
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UINT8 DeepS5DelayTime;
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} EFI_PLATFORM_DEEPS5_DATA;
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typedef struct {
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UINT8 EnableClockSpreadSpec;
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} EFI_PLATFORM_EXTERNAL_CLOCK;
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///
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/// Enumeration of possible Wilson City interposer types
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///
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typedef enum {
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InterposerUnknown = 0, ///< Type is unknown and should be retrieved from the Platform HOB
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InterposerA, ///< Interposer Type A
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InterposerB, ///< Interposer Type B
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InterposerMax ///< Maximum number of members of this enum
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} INTERPOSER_TYPE;
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#pragma pack(1)
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typedef struct {
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UINT8 MappedMcId[MAX_IMC];
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} INTERPOSER;
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typedef struct {
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INTERPOSER Interposer[InterposerMax];
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} INTERPOSER_MAP;
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#pragma pack()
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//
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// This HOB definition must be consistent with what is created in the
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// PlatformInfo protocol definition. This way the information in the
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// HOB can be directly copied upon the protocol and only the strings
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// will need to be updated.
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//
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typedef struct _EFI_PLATFORM_INFO {
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UINT8 SystemUuid[16]; // 16 bytes
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CHAR8 SerialNumber[64]; // 64 bytes
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UINT32 Signature; // "$PIT" 0x54495024
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UINT32 Size; // Size of the table
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UINT16 Revision; // Revision of the table
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UINT16 Type; // Platform Type
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UINT32 CpuType; // Cpu Type
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UINT8 CpuStepping; // Cpu Stepping
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UINT32 TypeRevisionId; // Board Revision ID
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UINT8 BoardId; // Board ID
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UINT16 IioSku;
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UINT16 IioRevision;
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UINT16 PchSku;
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UINT8 PchRevision;
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UINT8 PchType; // Retrive PCH SKU type installed
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UINT8 MaxNumOfPchs; // Maximum Number of installed PCHs
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BOOLEAN ExtendedInfoValid; // If TRUE then below fields are Valid
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UINT8 Checksum; // Checksum minus SystemUuid is valid in DXE only.
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UINT64 TypeStringPtr;
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UINT64 IioStringPtr;
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UINT64 PchStringPtr;
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EFI_PLATFORM_PCI_DATA PciData;
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EFI_PLATFORM_CPU_DATA CpuData;
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EFI_PLATFORM_MEM_DATA MemData;
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EFI_PLATFORM_SYS_DATA SysData;
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EFI_PLATFORM_PCH_DATA PchData;
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UINT8 IioRiserId;
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UINT8 PcieRiser1Type;
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UINT8 PcieRiser2Type;
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UINT8 PlatformCapabilities; // Platform capabilites describes platform is 2-socket modular board, 4S or 8S
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//
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// Wilson City Interposer Type
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//
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INTERPOSER_TYPE InterposerType[MAX_SOCKET]; // 0 - Unknown, 1 - InterposerA, 2 - InterposerB
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UINT32 QATDis; // 0 - QAT Enabled; 1 - Disabled
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UINT32 QATSel;
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UINT8 MemoryTopology[MAX_SOCKET][MAX_IMC*MAX_MC_CH]; // Specifies the memory topology per socket-per channel
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UINT8 MemoryConnectorType[MAX_SOCKET][MAX_IMC*MAX_MC_CH]; // Specifies the memory connector type per socket-per channel, type EFI_MEMORY_DIMM_CONNECTOR_TYPE
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EFI_PLATFORM_DEEPS5_DATA DeepS5Data;
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EFI_PLATFORM_EXTERNAL_CLOCK ExternalClock;
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} EFI_PLATFORM_INFO;
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#pragma pack()
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#endif // #ifndef _PLATFORM_INFO_H_
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