/** @file
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Intel CPU PPM policy common structures and macros for both PPM policy PPI and
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policy protocol.
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@copyright
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Copyright 2019 - 2021 Intel Corporation. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef __PPM_POLICY_PEI_DXE_COMMON_HEADER__
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#define __PPM_POLICY_PEI_DXE_COMMON_HEADER__
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/*===============================================================
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!!! Keep this file common for both PEI and DXE use !!!
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===============================================================*/
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#include <CpuDataStruct.h>
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#define NUM_CST_LAT_MSR 3
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#define NUM_TURBO_RATIO_GROUP 8
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//
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// Hardware P States Modes
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//
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typedef enum {
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HWP_MODE_DISABLED = 0, // also known as legacy P states
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HWP_MODE_NATIVE = 1, // native with legacy support
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HWP_MODE_OOB = 2, // out of band
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HWP_MODE_NATIVE_NO_LEGACY = 3 // native w/o legacy support
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} HWP_MODES;
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//
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// Power Perf Tuning options
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//
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// HWP is disabled : OS, BIOS and PECI control all available. OS control is the default
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// HWP native mode : OS, BIOS and PECI control all available. OS control is the default
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// HWP is OOB : BIOS and PECI control available. PECI control is the default
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// HWP is native w/o legacy: BIOS and PECI control available. BIOS control is the default
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//
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// On CPX, PECI is not available
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//
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typedef enum {
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PWR_PERF_TUNING_OS_CONTROL = 0,
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PWR_PERF_TUNING_BIOS_CONTROL = 1,
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PWR_PERF_TUNING_PECI_CONTROL = 2
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} POWER_PERF_TUNING_CONTROL;
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#pragma pack(1)
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typedef struct {
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UINT8 PkgCstEntryValCtl;
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UINT8 SapmctlValCtl;
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UINT8 SkipPkgCstEntry;
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UINT8 SwLtrOvrdCtl;
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UINT8 PriPlnCurrCfgCtl;
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UINT8 CurrentConfig;
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UINT8 MsrLock;
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UINT8 MsrPkgCstConfigControlLock;
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UINT8 MpllOffEnaAuto;
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UINT8 DynamicL1Disable;
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UINT8 VccsaVccioDisable;
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UINT8 PcodeWdogTimerEn;
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UINT8 DramRaplPwrLimitLockCsr;
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UINT8 EnableLowerLatencyMode;
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} ADV_PWR_CTL;
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typedef struct {
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UINT8 BidirProchotEnable;
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UINT8 C1eEnable;
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UINT8 EeTurboDisable;
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UINT8 ProchotOutputDisable;
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UINT8 SapmControl;
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UINT8 PwrPerfSwitch;
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POWER_PERF_TUNING_CONTROL PwrPerfTuning;
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UINT8 ProchotLock;
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UINT8 LtrSwInput;
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UINT8 PkgCLatNeg;
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UINT8 SetvidDecayDisable;
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} POWER_CTL;
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typedef struct {
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UINT16 PowerLimit1Power;
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UINT8 PowerLimit1En;
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UINT16 PowerLimit1Time;
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UINT8 PkgClmpLim1;
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UINT16 PowerLimit2Power;
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UINT8 PkgClmpLim2;
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UINT8 PowerLimit2En;
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UINT16 PowerLimit2Time;
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UINT8 TurboPowerLimitLock;
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UINT8 TurboLimitCsrLock;
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} TURBO_POWRER_LIMIT;
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typedef struct {
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UINT16 CurrentLimit;
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UINT8 PpcccLock;
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} PPO_CURRENT_CFG;
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typedef struct {
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UINT8 WorkLdConfig;
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UINT8 AltEngPerfBIAS;
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UINT8 P0TtlTimeHigh1;
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UINT8 P0TtlTimeLow1;
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UINT16 EngAvgTimeWdw1;
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} PERF_BIAS_CONFIG;
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typedef struct {
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UINT8 PmaxDetector;
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UINT8 PmaxAutoAdjustment;
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UINT8 PmaxLoadLine;
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UINT8 PmaxSign;
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UINT8 PmaxOffset;
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UINT8 PmaxOffsetNegative;
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UINT8 PmaxTriggerSetup;
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UINT16 BasePackageTdp[MAX_SOCKET];
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UINT8 EnhancedPmaxDetector;
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} PMAX_CONFIG;
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typedef struct {
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UINT8 Iio0PkgcClkGateDis;
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UINT8 Iio1PkgcClkGateDis;
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UINT8 Iio2PkgcClkGateDis;
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UINT8 Kti01PkgcClkGateDis;
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UINT8 Kti23PkgcClkGateDis;
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UINT8 Kti45PkgcClkGateDis;
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UINT8 Mc0PkgcClkGateDis;
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UINT8 Mc1PkgcClkGateDis;
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UINT8 P0pllOffEna;
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UINT8 P1pllOffEna;
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UINT8 P2pllOffEna;
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UINT8 Kti01pllOffEna;
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UINT8 Kti23pllOffEna;
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UINT8 Kti45pllOffEna;
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UINT8 Mc0pllOffEna;
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UINT8 Mc1pllOffEna;
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UINT8 Mc0PkgcIoVolRedDis;
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UINT8 Mc1PkgcIoVolRedDis;
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UINT8 Mc0PkgcDigVolRedDis;
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UINT8 Mc1PkgcDigVolRedDis;
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UINT8 SetvidDecayDisable;
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UINT8 SapmCtlLock;
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} SAPM_CTL;
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typedef struct {
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UINT8 PerfPLimitEn;
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UINT8 PerfPLmtThshld;
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UINT8 PerfPLimitClipC;
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UINT8 PerfPlimitDifferential;
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} PERF_PLIMIT_CTL;
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typedef struct {
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UINT8 KtiApmOvrdEn;
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UINT8 IomApmOvrdEn;
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UINT8 IoBwPlmtOvrdEn;
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UINT8 EetOverrideEn;
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UINT8 UncrPerfPlmtOvrdEn;
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} DYNAMIC_PER_POWER_CTL;
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typedef struct {
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UINT16 NonSnpLatVal;
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UINT8 NonSnpLatMult;
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UINT8 NonSnpLatOvrd;
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UINT16 NonSnpLatVld;
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UINT16 SnpLatVal;
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UINT8 SnpLatMult;
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UINT8 SnpLatOvrd;
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UINT8 SnpLatVld;
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} PCIE_ILTR_OVRD;
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typedef struct {
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UINT16 Value;
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UINT8 Multiplier;
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UINT8 Valid;
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} CST_LATENCY_CTL;
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typedef struct {
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BOOLEAN C1e;
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UINT32 PkgCstEntryCriteriaMaskKti[MAX_SOCKET];
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UINT32 PkgCstEntryCriteriaMaskPcie[MAX_SOCKET];
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CST_LATENCY_CTL LatencyCtrl[NUM_CST_LAT_MSR];
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} PPM_CSTATE_STRUCT;
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typedef struct {
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BOOLEAN Enable;
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UINT32 Voltage;
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UINT16 RatioLimit[MAX_CORE];
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} PPM_XE_STRUCT;
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typedef struct {
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UINT8 RatioLimitRatio[NUM_TURBO_RATIO_GROUP];
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UINT8 RatioLimitRatioMask[NUM_TURBO_RATIO_GROUP];
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UINT8 RatioLimitCores[NUM_TURBO_RATIO_GROUP];
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UINT8 RatioLimitCoresMask[NUM_TURBO_RATIO_GROUP];
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} TURBO_RATIO_LIMIT;
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typedef struct {
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HWP_MODES HWPMEnable;
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UINT8 HWPMNative;
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UINT8 HWPMOOB;
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UINT8 HWPMInterrupt;
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UINT8 EPPEnable;
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UINT8 EPPProfile;
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UINT8 APSrocketing;
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UINT8 Scalability;
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UINT8 PPOTarget;
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UINT8 RaplPrioritization;
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UINT32 SstCpSystemStatus;
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UINT8 OutofBandAlternateEPB;
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UINT8 ConfigurePbf;
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UINT64 PbfHighPriCoreMap[MAX_SOCKET]; // PBF High Priority Cores Bitmap
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UINT8 PbfP1HighRatio[MAX_SOCKET]; // PBF P1_High Ratio
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UINT8 PbfP1LowRatio[MAX_SOCKET]; // PBF P1_Low Ratio
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} PPM_HWPM_STRUCT;
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typedef struct {
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UINT8 EnablePkgcCriteria;
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UINT8 EnablePkgCCriteriaKti[MAX_SOCKET];
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UINT8 EnablePkgCCriteriaRlink[MAX_SOCKET];
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UINT8 EnablePkgCCriteriaFxr[MAX_SOCKET];
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UINT8 EnablePkgCCriteriaMcddr[MAX_SOCKET];
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UINT8 EnablePkgCCriteriaHbm[MAX_SOCKET];
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UINT8 EnablePkgCCriteriaIio[MAX_SOCKET];
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UINT8 EnablePkgCCriteriaHqm[MAX_SOCKET];
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UINT8 EnablePkgCCriteriaNac[MAX_SOCKET];
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UINT8 EnablePkgCCriteriaTip[MAX_SOCKET];
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UINT8 EnablePkgCCriteriaMdfs[MAX_SOCKET];
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UINT8 EnablePkgCCriteriaHcx[MAX_SOCKET];
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UINT8 EnablePkgCCriteriaDino[MAX_SOCKET];
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UINT8 PkgCCriteriaLogicalIpType[MAX_SOCKET];
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UINT8 PkgCCriteriaLogicalIpTypeMcddr[MAX_SOCKET];
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UINT8 PkgCCriteriaLogicalIpTypeHbm[MAX_SOCKET];
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UINT8 PkgCCriteriaLogicalIpTypeIio[MAX_SOCKET];
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UINT8 PkgCCriteriaInstanceNoKti[MAX_SOCKET];
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UINT8 EnableLinkInL1Kti[MAX_SOCKET];
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UINT8 PkgCCriteriaInstanceNoRlink[MAX_SOCKET];
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UINT8 EnableLinkInL1Rlink[MAX_SOCKET];
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UINT8 PkgCCriteriaInstanceNoFxr[MAX_SOCKET];
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UINT8 PkgcCriteraPsMaskFxr[MAX_SOCKET];
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UINT8 PkgCCriteriaAllowedPsMaskFxr[MAX_SOCKET];
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UINT8 PkgCCriteriaInstanceNoMcddr[MAX_SOCKET];
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UINT8 PkgcCriteriaPsOptionMcddr[MAX_SOCKET];
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UINT8 PkgCCriteriaInstanceNoHbm[MAX_SOCKET];
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UINT8 PkgcCriteriaPsOptionHbm[MAX_SOCKET];
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UINT8 PkgCCriteriaInstanceNoIio[MAX_SOCKET];
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UINT8 EnableLinkInL1Iio[MAX_SOCKET];
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UINT8 PkgCCriteriaInstanceNoHqm[MAX_SOCKET];
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UINT8 PkgcCriteraPsMaskHqm[MAX_SOCKET];
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UINT8 PkgCCriteriaAllowedPsMaskHqm[MAX_SOCKET];
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UINT8 PkgCCriteriaInstanceNoNac[MAX_SOCKET];
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UINT8 PkgcCriteraPsMaskNac[MAX_SOCKET];
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UINT8 PkgCCriteriaAllowedPsMaskNac[MAX_SOCKET];
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UINT8 PkgCCriteriaInstanceNoTip[MAX_SOCKET];
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UINT8 PkgcCriteraPsMaskTip[MAX_SOCKET];
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UINT8 PkgCCriteriaAllowedPsMaskTip[MAX_SOCKET];
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UINT8 PkgCCriteriaInstanceNoMdfs[MAX_SOCKET];
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UINT8 AllowLpStateMdfs[MAX_SOCKET];
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UINT8 PkgCCriteriaInstanceNoHcx[MAX_SOCKET];
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UINT8 PkgcCriteraPsMaskHcx[MAX_SOCKET];
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UINT8 PkgCCriteriaAllowedPsMaskHcx[MAX_SOCKET];
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UINT8 PkgCCriteriaInstanceNoDino[MAX_SOCKET];
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UINT8 PkgcCriteraPsMaskDino[MAX_SOCKET];
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UINT8 PkgCCriteriaAllowedPsMaskDino[MAX_SOCKET];
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} PKGC_SA_PS_CRITERIA_STRUCT;
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typedef struct {
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UINT8 ThermalMonitorStatusFilter;
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UINT8 ThermalMonitorStatusFilterTimeWindow;
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} TM_STATUS_Filter;
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typedef struct {
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UINT8 IssCapableSystem;
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UINT8 DynamicIss;
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UINT8 ConfigTDPLevel;
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UINT8 ConfigTDPLock;
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UINT16 CurrentPackageTdp[MAX_SOCKET];
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UINT8 FastRaplDutyCycle;
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UINT32 ProchotRatio;
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UINT8 OverclockingLock;
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UINT32 C2C3TT;
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UINT8 AvxSupport;
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UINT8 AvxLicensePreGrant;
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UINT8 AvxIccpLevel;
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UINT8 GpssTimer;
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ADV_PWR_CTL AdvPwrMgtCtl;
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POWER_CTL PowerCtl;
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TURBO_POWRER_LIMIT TurboPowerLimit;
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PPO_CURRENT_CFG PpoCurrentCfg;
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PERF_BIAS_CONFIG PerfBiasConfig;
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PMAX_CONFIG PmaxConfig;
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TM_STATUS_Filter ThermalReport;
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SAPM_CTL SapmCtl[MAX_SOCKET];
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PERF_PLIMIT_CTL PerPLimitCtl;
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DYNAMIC_PER_POWER_CTL DynamicPerPowerCtl;
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PCIE_ILTR_OVRD PcieIltrOvrd;
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PPM_CSTATE_STRUCT PpmCst;
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PPM_XE_STRUCT PpmXe;
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PPM_HWPM_STRUCT Hwpm;
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TURBO_RATIO_LIMIT TurboRatioLimit;
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PKGC_SA_PS_CRITERIA_STRUCT PkgcCriteria;
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UINT8 CpuThermalManagement;
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UINT8 RunCpuPpmInPei;
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} PPM_POLICY_CONFIGURATION;
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#pragma pack()
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#endif
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