/** @file
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Intel CPU PPM policy common structures and macros for both
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CPU late policy PPI and CPU policy protocol.
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@copyright
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Copyright 2020 - 2021 Intel Corporation. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef __CPU_POLICY_PEI_DXE_COMMON_HEADER__
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#define __CPU_POLICY_PEI_DXE_COMMON_HEADER__
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typedef struct {
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BOOLEAN CpuTStateEnable;
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UINT8 CpuClockModulationDutyCycle;
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BOOLEAN CpuAesEnable;
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BOOLEAN CpuFastStringEnable;
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BOOLEAN CpuMaxCpuidValueLimitEnable;
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BOOLEAN CpuMachineCheckEnable;
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BOOLEAN CpuMonitorMwaitEnable;
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BOOLEAN CpuVtEnable;
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BOOLEAN CpuLtEnable;
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BOOLEAN CpuX2ApicEnable;
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BOOLEAN CpuEistEnable;
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BOOLEAN CpuTurboModeEnable;
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BOOLEAN CpuHwCoordinationEnable;
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UINT8 CpuBootPState;
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BOOLEAN CpuPpinControlEnable;
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BOOLEAN CpuPeciDownstreamWriteEnable;
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BOOLEAN CpuL1NextPagePrefetcherDisable;
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BOOLEAN CpuDcuPrefetcherEnable;
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BOOLEAN CpuIpPrefetcherEnable;
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BOOLEAN CpuMlcStreamerPrefetecherEnable;
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BOOLEAN CpuMlcSpatialPrefetcherEnable;
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BOOLEAN CpuAmpPrefetchEnable;
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BOOLEAN CpuThreeStrikeCounterEnable;
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BOOLEAN CpuCStateEnable;
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UINT8 CpuPackageCStateLimit;
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BOOLEAN CpuC1AutoDemotionEnable;
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BOOLEAN CpuC1AutoUndemotionEnable;
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UINT8 CpuCoreCStateValue;
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UINT16 CpuAcpiLvl2Addr;
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BOOLEAN CpuThermalManagementEnable;
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UINT8 CpuTccActivationOffset;
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BOOLEAN CpuDbpfEnable;
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BOOLEAN CpuEnergyPerformanceBiasEnable;
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UINT32 CpuIioLlcWaysBitMask;
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UINT32 CpuExpandedIioLlcWaysBitMask;
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UINT32 CpuRemoteWaysBitMask;
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UINT32 CpuRrqCountThreshold;
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UINT8 CpuMtoIWa;
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BOOLEAN RunCpuPpmInPei;
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BOOLEAN AcExceptionOnSplitLockEnable;
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BOOLEAN CpuCrashLogGprs;
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} CPU_POLICY_COMMON;
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#endif
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