/** @file
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CPU PCIe SMM Driver Entry
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Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "SaLateInitSmm.h"
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#include <Library/BaseLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/UefiBootServicesTableLib.h>
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#include <Library/DxeServicesTableLib.h>
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#include <Library/SmmServicesTableLib.h>
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#include <PcieRegs.h>
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#include <Register/PchRegs.h>
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#include <Register/CpuPcieRegs.h>
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#include <Library/PcieHelperLib.h>
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#include <CpuPcieInfo.h>
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#include <Library/TimerLib.h>
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#include <Library/PciExpressHelpersLib.h>
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#include <Library/CpuPcieInfoFruLib.h>
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#include <CpuPcieConfig.h>
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#include <Library/CpuPcieRpLib.h>
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#include <Protocol/PchPcieSmiDispatch.h>
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#include <Protocol/PchSmiDispatch.h>
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#include <Protocol/SaIotrapSmi.h>
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#include <Library/SmmServicesTableLib.h>
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#include <Library/S3BootScriptLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <CpuPcieHob.h>
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GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mSaBusNumber;
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//
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// @note:
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// These temp bus numbers cannot be used in runtime (hot-plug).
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// These can be used only during boot.
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//
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GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mTempRootPortBusNumMin;
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GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mTempRootPortBusNumMax;
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GLOBAL_REMOVE_IF_UNREFERENCED CPU_PCIE_ROOT_PORT_CONFIG mCpuPcieRootPortConfig[CPU_PCIE_MAX_ROOT_PORTS];
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GLOBAL_REMOVE_IF_UNREFERENCED BOOLEAN mCpuPciePmTrapExecuted = FALSE;
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GLOBAL_REMOVE_IF_UNREFERENCED PCH_PCIE_DEVICE_OVERRIDE *mDevAspmOverride;
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GLOBAL_REMOVE_IF_UNREFERENCED UINT32 mNumOfDevAspmOverride;
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/**
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An IoTrap callback to config PCIE power management settings
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**/
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VOID
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CpuPciePmIoTrapSmiCallback (
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VOID
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)
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{
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UINT32 PortIndex;
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UINT64 RpBase;
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UINT8 MaxPciePortNum;
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UINTN RpDevice;
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UINTN RpFunction;
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MaxPciePortNum = GetMaxCpuPciePortNum ();
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for (PortIndex = 0; PortIndex < MaxPciePortNum; PortIndex++) {
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GetCpuPcieRpDevFun (PortIndex, &RpDevice, &RpFunction);
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RpBase = PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, SA_MC_BUS, (UINT32) RpDevice, (UINT32) RpFunction, 0);
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if (PciSegmentRead16 (RpBase) != 0xFFFF) {
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mDevAspmOverride = NULL;
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mNumOfDevAspmOverride = 0;
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RootportDownstreamPmConfiguration (
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SA_SEG_NUM,
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SA_MC_BUS,
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(UINT8)RpDevice,
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(UINT8)RpFunction,
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mTempRootPortBusNumMin,
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mTempRootPortBusNumMax,
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&mCpuPcieRootPortConfig[PortIndex].PcieRpCommonConfig,
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mNumOfDevAspmOverride,
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mDevAspmOverride
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);
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}
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}
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}
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/**
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Program Common Clock and ASPM of Downstream Devices
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@param[in] PortIndex Pcie Root Port Number
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@param[in] RpDevice Pcie Root Pci Device Number
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@param[in] RpFunction Pcie Root Pci Function Number
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@retval EFI_SUCCESS Root port complete successfully
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@retval EFI_UNSUPPORTED PMC has invalid vendor ID
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**/
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EFI_STATUS
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CpuPcieSmi (
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IN UINT8 PortIndex,
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IN UINT8 RpDevice,
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IN UINT8 RpFunction
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)
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{
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UINT8 SecBus;
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UINT8 SubBus;
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UINT64 RpBase;
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UINT64 EpBase;
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UINT8 EpPcieCapPtr;
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UINT8 EpMaxSpeed;
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BOOLEAN DownstreamDevicePresent;
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UINT32 Timeout;
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UINT32 MaxLinkSpeed;
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RpBase = PCI_SEGMENT_LIB_ADDRESS (
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SA_SEG_NUM,
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SA_MC_BUS,
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(UINT32) RpDevice,
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(UINT32) RpFunction,
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0
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);
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if (PciSegmentRead16 (RpBase + PCI_VENDOR_ID_OFFSET) == 0xFFFF) {
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DEBUG((DEBUG_INFO, "PCIe controller is disabled, return!!\n"));
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return EFI_SUCCESS;
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}
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//
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// Check presence detect state. Here the endpoint must be detected using PDS rather than
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// the usual LinkActive check, because PDS changes immediately and LA takes a few milliseconds to stabilize
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//
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DownstreamDevicePresent = !!(PciSegmentRead16 (RpBase + R_PCIE_SLSTS) & B_PCIE_SLSTS_PDS);
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if (DownstreamDevicePresent) {
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///
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/// Make sure the link is active before trying to talk to device behind it
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/// Wait up to 100ms, according to PCIE spec chapter 6.7.3.3
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///
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Timeout = 100 * 1000;
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while (CpuPcieIsLinkActive(RpBase) == 0) {
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MicroSecondDelay (10);
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Timeout-=10;
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if (Timeout == 0) {
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DEBUG((DEBUG_INFO, "PDS set but timeout while waiting for LA bit to get set!!!\n"));
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return EFI_NOT_FOUND;
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}
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}
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SecBus = PciSegmentRead8 (RpBase + PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET);
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SubBus = PciSegmentRead8 (RpBase + PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET);
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ASSERT (SecBus != 0 && SubBus != 0);
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if (SecBus == 0) {
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DEBUG((DEBUG_INFO, "Secondary Bus is 0, return!!!\n"));
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return EFI_NOT_FOUND;
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}
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RootportDownstreamConfiguration (
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SA_SEG_NUM,
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SA_MC_BUS,
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RpDevice,
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RpFunction,
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mTempRootPortBusNumMin,
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mTempRootPortBusNumMax,
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EnumCpuPcie
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);
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RootportDownstreamPmConfiguration (
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SA_SEG_NUM,
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SA_MC_BUS,
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RpDevice,
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RpFunction,
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mTempRootPortBusNumMin,
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mTempRootPortBusNumMax,
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&mCpuPcieRootPortConfig[PortIndex].PcieRpCommonConfig,
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mNumOfDevAspmOverride,
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mDevAspmOverride
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);
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//
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// Perform Equalization
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//
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EpBase = PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, SecBus, 0, 0, 0);
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EpPcieCapPtr = PcieFindCapId (SA_SEG_NUM, SecBus, 0, 0, EFI_PCI_CAPABILITY_ID_PCIEXP);
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EpMaxSpeed = PciSegmentRead8 (EpBase + EpPcieCapPtr + R_PCIE_LCAP_OFFSET) & B_PCIE_LCAP_MLS;
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MaxLinkSpeed = CpuPcieGetMaxLinkSpeed (RpBase);
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if (EpMaxSpeed < MaxLinkSpeed) {
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MaxLinkSpeed = EpMaxSpeed;
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}
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if (EpMaxSpeed >= V_PCIE_LCAP_MLS_GEN3 && EpMaxSpeed <= V_PCIE_LCAP_MLS_GEN4) {
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PciSegmentAndThenOr16 (RpBase + R_PCIE_LCTL2, (UINT16)~B_PCIE_LCTL2_TLS, (UINT16)MaxLinkSpeed);
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PciSegmentOr32 (RpBase + R_PCIE_LCTL3, B_PCIE_LCTL3_PE);
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PciSegmentOr32 (RpBase + R_PCIE_LCTL, B_PCIE_LCTL_RL);
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}
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}
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return EFI_SUCCESS;
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}
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/**
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PCIE Hotplug SMI call back function for each Root port
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@param[in] DispatchHandle Handle of this dispatch function
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@param[in] RpContext Rootport context, which contains RootPort Index,
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and RootPort PCI BDF.
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**/
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VOID
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EFIAPI
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CpuPcieSmiRpHandlerFunction (
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IN EFI_HANDLE DispatchHandle,
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IN PCH_PCIE_SMI_RP_CONTEXT *RpContext
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)
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{
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CpuPcieSmi (RpContext->RpIndex, RpContext->DevNum, RpContext->FuncNum);
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}
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/**
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PCIE Link Active State Change Hotplug SMI call back function for all Root ports
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@param[in] DispatchHandle Handle of this dispatch function
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@param[in] RpContext Rootport context, which contains RootPort Index,
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and RootPort PCI BDF.
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**/
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VOID
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EFIAPI
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CpuPcieLinkActiveStateChange (
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IN EFI_HANDLE DispatchHandle,
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IN PCH_PCIE_SMI_RP_CONTEXT *RpContext
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)
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{
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return;
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}
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/**
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PCIE Link Equalization Request SMI call back function for all Root ports
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@param[in] DispatchHandle Handle of this dispatch function
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@param[in] RpContext Rootport context, which contains RootPort Index,
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and RootPort PCI BDF.
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**/
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VOID
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EFIAPI
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CpuPcieLinkEqHandlerFunction (
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IN EFI_HANDLE DispatchHandle,
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IN PCH_PCIE_SMI_RP_CONTEXT *RpContext
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)
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{
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///
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/// From PCI Express specification, the PCIe device can request for Link Equalization. When the
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/// Link Equalization is requested by the device, an SMI will be generated by PCIe RP when
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/// enabled and the SMI subroutine would invoke the Software Preset/Coefficient Search
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/// software to re-equalize the link.
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///
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return;
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}
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/**
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An IoTrap callback to config PCIE power management settings
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@param[in] DispatchHandle - The handle of this callback, obtained when registering
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@param[in] DispatchContext - Pointer to the EFI_SMM_IO_TRAP_DISPATCH_CALLBACK_CONTEXT
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**/
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VOID
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EFIAPI
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CpuPcieIoTrapSmiCallback (
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IN EFI_HANDLE DispatchHandle,
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IN EFI_SMM_IO_TRAP_CONTEXT *CallbackContext,
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IN OUT VOID *CommBuffer,
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IN OUT UINTN *CommBufferSize
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)
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{
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if (CallbackContext->WriteData == CpuPciePmTrap) {
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if (mCpuPciePmTrapExecuted == FALSE) {
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CpuPciePmIoTrapSmiCallback ();
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mCpuPciePmTrapExecuted = TRUE;
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}
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} else {
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ASSERT_EFI_ERROR (EFI_INVALID_PARAMETER);
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}
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}
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/**
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This function clear the Io trap executed flag before enter S3
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@param[in] Handle Handle of the callback
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@param[in] Context The dispatch context
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@retval EFI_SUCCESS SA register saved
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**/
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EFI_STATUS
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EFIAPI
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CpuPcieS3EntryCallBack (
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IN EFI_HANDLE Handle,
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IN CONST VOID *Context OPTIONAL,
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IN OUT VOID *CommBuffer OPTIONAL,
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IN OUT UINTN *CommBufferSize OPTIONAL
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)
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{
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mCpuPciePmTrapExecuted = FALSE;
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return EFI_SUCCESS;
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}
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/**
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Register PCIE Hotplug SMI dispatch function to handle Hotplug enabling
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@param[in] ImageHandle The image handle of this module
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@param[in] SystemTable The EFI System Table
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@retval EFI_SUCCESS The function completes successfully
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**/
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EFI_STATUS
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EFIAPI
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InitializeCpuPcieSmm (
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IN EFI_HANDLE ImageHandle,
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IN EFI_SYSTEM_TABLE *SystemTable
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)
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{
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EFI_STATUS Status;
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UINT8 PortIndex;
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UINT8 Data8;
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UINT32 Data32Or;
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UINT32 Data32And;
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UINT64 RpBase;
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UINTN RpDevice;
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UINTN RpFunction;
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EFI_HANDLE PcieHandle;
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EFI_HANDLE PchIoTrapHandle;
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PCH_PCIE_SMI_DISPATCH_PROTOCOL *PchPcieSmiDispatchProtocol;
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EFI_SMM_IO_TRAP_REGISTER_CONTEXT PchIoTrapContext;
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EFI_SMM_SX_REGISTER_CONTEXT SxDispatchContext;
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SA_IOTRAP_SMI_PROTOCOL *CpuPcieIoTrapProtocol;
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EFI_HANDLE SxDispatchHandle;
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UINT8 MaxPciePortNum;
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CPU_PCIE_HOB *CpuPcieHob;
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DEBUG ((DEBUG_INFO, "InitializeCpuPcieSmm () Start\n"));
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MaxPciePortNum = GetMaxCpuPciePortNum ();
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//
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// Locate Pch Pcie Smi Dispatch Protocol
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//
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Status = gSmst->SmmLocateProtocol (&gPchPcieSmiDispatchProtocolGuid, NULL, (VOID**) &PchPcieSmiDispatchProtocol);
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ASSERT_EFI_ERROR (Status);
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mTempRootPortBusNumMin = PcdGet8 (PcdSiliconInitTempPciBusMin);
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mTempRootPortBusNumMax = PcdGet8 (PcdSiliconInitTempPciBusMax);
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///
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/// Locate HOB for CPU PCIe
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///
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CpuPcieHob = GetFirstGuidHob(&gCpuPcieHobGuid);
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if (CpuPcieHob != NULL) {
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ASSERT (sizeof mCpuPcieRootPortConfig == sizeof CpuPcieHob->RootPort);
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CopyMem (
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mCpuPcieRootPortConfig,
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&(CpuPcieHob->RootPort),
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sizeof (mCpuPcieRootPortConfig)
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);
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}
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//
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// Throught all PCIE root port function and register the SMI Handler for enabled ports.
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//
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for (PortIndex = 0; PortIndex < MaxPciePortNum; PortIndex++) {
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GetCpuPcieRpDevFun (PortIndex, &RpDevice, &RpFunction);
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RpBase = PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, SA_MC_BUS, (UINT32) RpDevice, (UINT32) RpFunction, 0);
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//
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// Skip the root port function which is not enabled
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//
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if (PciSegmentRead32 (RpBase) == 0xFFFFFFFF) {
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continue;
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}
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//
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// Register SMI Handlers for Hot Plug and Link Active State Change
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//
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Data8 = PciSegmentRead8 (RpBase + R_PCIE_SLCAP);
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if (Data8 & B_PCIE_SLCAP_HPC) {
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PcieHandle = NULL;
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Status = PchPcieSmiDispatchProtocol->HotPlugRegister (
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PchPcieSmiDispatchProtocol,
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CpuPcieSmiRpHandlerFunction,
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(PortIndex + CpuRpIndex0),
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&PcieHandle
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);
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ASSERT_EFI_ERROR (Status);
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Status = PchPcieSmiDispatchProtocol->LinkActiveRegister (
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PchPcieSmiDispatchProtocol,
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CpuPcieLinkActiveStateChange,
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(PortIndex + CpuRpIndex0),
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&PcieHandle
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);
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ASSERT_EFI_ERROR (Status);
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Data32Or = B_PCIE_MPC_HPME;
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Data32And = (UINT32) ~B_PCIE_MPC_HPME;
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S3BootScriptSaveMemReadWrite (
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S3BootScriptWidthUint32,
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PcdGet64 (PcdSiPciExpressBaseAddress) + RpBase + R_PCIE_MPC,
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&Data32Or, /// Data to be ORed
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&Data32And /// Data to be ANDed
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);
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}
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//
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// Register SMI Handler for Link Equalization Request from Gen 3 Devices.
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//
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Data8 = PciSegmentRead8 (RpBase + R_PCIE_LCAP);
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if ((Data8 & B_PCIE_LCAP_MLS) == V_PCIE_LCAP_MLS_GEN3) {
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Status = PchPcieSmiDispatchProtocol->LinkEqRegister (
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PchPcieSmiDispatchProtocol,
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CpuPcieLinkEqHandlerFunction,
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(PortIndex + CpuRpIndex0),
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&PcieHandle
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);
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ASSERT_EFI_ERROR (Status);
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}
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}
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ASSERT_EFI_ERROR (Status);
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PchIoTrapContext.Type = WriteTrap;
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PchIoTrapContext.Length = 4;
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PchIoTrapContext.Address = 0;
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Status = mPchIoTrap->Register (
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mPchIoTrap,
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(EFI_SMM_HANDLER_ENTRY_POINT2) CpuPcieIoTrapSmiCallback,
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&PchIoTrapContext,
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&PchIoTrapHandle
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);
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ASSERT_EFI_ERROR (Status);
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//
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// Install the SA Pcie IoTrap protocol
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//
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(gBS->AllocatePool) (EfiBootServicesData, sizeof (SA_IOTRAP_SMI_PROTOCOL), (VOID **)&CpuPcieIoTrapProtocol);
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CpuPcieIoTrapProtocol->SaIotrapSmiAddress = PchIoTrapContext.Address;
|
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Status = gBS->InstallMultipleProtocolInterfaces (
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&ImageHandle,
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&gCpuPcieIoTrapProtocolGuid,
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CpuPcieIoTrapProtocol,
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NULL
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);
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//
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// Register the callback for S3 entry
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//
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SxDispatchContext.Type = SxS3;
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SxDispatchContext.Phase = SxEntry;
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Status = mSxDispatch->Register (
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mSxDispatch,
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CpuPcieS3EntryCallBack,
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&SxDispatchContext,
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&SxDispatchHandle
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);
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ASSERT_EFI_ERROR (Status);
|
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DEBUG ((DEBUG_INFO, "InitializeCpuPcieSmm, IoTrap @ %x () End\n", PchIoTrapContext.Address));
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return EFI_SUCCESS;
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}
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