/** @file
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This is the driver that initializes the Intel System Agent.
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Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "SaInitDxe.h"
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#include "SaInit.h"
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#include <SaConfigHob.h>
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#include <Protocol/SaNvsArea.h>
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#include <Library/PchInfoLib.h>
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#include <CpuPcieInfo.h>
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#include <Library/DxeCpuPcieRpLib.h>
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#include <SaConfigHob.h>
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#include <CpuPcieHob.h>
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#include <HostBridgeDataHob.h>
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#include <CpuDataStruct.h>
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///
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/// Global Variables
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///
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GLOBAL_REMOVE_IF_UNREFERENCED SYSTEM_AGENT_NVS_AREA_PROTOCOL mSaNvsAreaProtocol;
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GLOBAL_REMOVE_IF_UNREFERENCED SA_POLICY_PROTOCOL *mSaPolicy;
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extern SA_CONFIG_HOB *mSaConfigHob;
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/**
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A protocol callback which updates 64bits MMIO Base and Length in SA GNVS area
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**/
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VOID
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UpdateSaGnvsForMmioResourceBaseLength (
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VOID
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)
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{
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EFI_PHYSICAL_ADDRESS PciBaseAddress;
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UINT32 Tolud;
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UINT64 Length;
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UINT64 McD0BaseAddress;
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UINTN ResMemLimit1;
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UINT8 EnableAbove4GBMmioBiosAssignemnt;
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HOST_BRIDGE_DATA_HOB *HostBridgeDataHob;
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PciBaseAddress = 0;
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Tolud = 0;
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Length = 0;
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ResMemLimit1 = 0;
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EnableAbove4GBMmioBiosAssignemnt = 0;
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HostBridgeDataHob = NULL;
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//
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// Read memory map registers
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//
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McD0BaseAddress = PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, SA_MC_BUS, 0, 0, 0);
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Tolud = PciSegmentRead32 (McD0BaseAddress + R_SA_TOLUD) & B_SA_TOLUD_TOLUD_MASK;
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PciBaseAddress = Tolud;
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ResMemLimit1 = (UINTN) PcdGet64 (PcdSiPciExpressBaseAddress);
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Length = ResMemLimit1 - PciBaseAddress;
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//
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// Get HostBridgeData HOB and see if above 4GB MMIO BIOS assignment enabled
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//
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HostBridgeDataHob = (HOST_BRIDGE_DATA_HOB *) GetFirstGuidHob (&gHostBridgeDataHobGuid);
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if ((HostBridgeDataHob != NULL) && (HostBridgeDataHob->EnableAbove4GBMmio == 1)) {
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EnableAbove4GBMmioBiosAssignemnt = 1;
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}
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//
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// Enable Above 4GB MMIO when Aperture Size is 2GB or higher
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//
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if ((mSaConfigHob != NULL) && (mSaConfigHob->ApertureSize >= 15)) {
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EnableAbove4GBMmioBiosAssignemnt = 1;
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}
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//
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// Check Enable Above 4GB MMIO or not
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//
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DEBUG ((DEBUG_INFO, "Update SA GNVS Area.\n"));
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mSaNvsAreaProtocol.Area->Mmio32Base = (UINT32) PciBaseAddress;
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mSaNvsAreaProtocol.Area->Mmio32Length = (UINT32) Length;
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if (EnableAbove4GBMmioBiosAssignemnt == 1) {
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mSaNvsAreaProtocol.Area->Mmio64Base = BASE_256GB;
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mSaNvsAreaProtocol.Area->Mmio64Length = SIZE_256GB;
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}
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DEBUG ((DEBUG_INFO, "SaNvsAreaProtocol.Area->Mmio64Base = %lx\n", mSaNvsAreaProtocol.Area->Mmio64Base));
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DEBUG ((DEBUG_INFO, "SaNvsAreaProtocol.Area->Mmio64Length = %lx\n", mSaNvsAreaProtocol.Area->Mmio64Length));
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DEBUG ((DEBUG_INFO, "SaNvsAreaProtocol.Area->Mmio32Base = %lx\n", mSaNvsAreaProtocol.Area->Mmio32Base));
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DEBUG ((DEBUG_INFO, "SaNvsAreaProtocol.Area->Mmio32Length = %lx\n", mSaNvsAreaProtocol.Area->Mmio32Length));
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}
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/**
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Install SSDT Table
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@retval EFI_SUCCESS - SSDT Table load successful.
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**/
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EFI_STATUS
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InstallSsdtAcpiTable (
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IN GUID SsdtTableGuid,
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IN UINT64 Signature
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)
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{
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EFI_STATUS Status;
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EFI_HANDLE *HandleBuffer;
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BOOLEAN LoadTable;
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UINTN NumberOfHandles;
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UINTN Index;
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INTN Instance;
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UINTN Size;
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UINT32 FvStatus;
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UINTN TableHandle;
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EFI_FV_FILETYPE FileType;
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EFI_FV_FILE_ATTRIBUTES Attributes;
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EFI_FIRMWARE_VOLUME2_PROTOCOL *FwVol;
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EFI_ACPI_TABLE_PROTOCOL *AcpiTable;
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EFI_ACPI_DESCRIPTION_HEADER *TableHeader;
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EFI_ACPI_COMMON_HEADER *Table;
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FwVol = NULL;
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Table = NULL;
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DEBUG ((DEBUG_INFO, "Loading SSDT Table GUID: %g\n", SsdtTableGuid));
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///
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/// Locate FV protocol.
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///
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Status = gBS->LocateHandleBuffer (
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ByProtocol,
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&gEfiFirmwareVolume2ProtocolGuid,
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NULL,
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&NumberOfHandles,
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&HandleBuffer
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);
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ASSERT_EFI_ERROR (Status);
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///
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/// Look for FV with ACPI storage file
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///
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for (Index = 0; Index < NumberOfHandles; Index++) {
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///
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/// Get the protocol on this handle
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/// This should not fail because of LocateHandleBuffer
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///
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Status = gBS->HandleProtocol (
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HandleBuffer[Index],
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&gEfiFirmwareVolume2ProtocolGuid,
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(VOID **) &FwVol
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);
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ASSERT_EFI_ERROR (Status);
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if (FwVol == NULL) {
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return EFI_NOT_FOUND;
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}
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///
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/// See if it has the ACPI storage file
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///
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Size = 0;
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FvStatus = 0;
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Status = FwVol->ReadFile (
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FwVol,
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&SsdtTableGuid,
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NULL,
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&Size,
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&FileType,
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&Attributes,
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&FvStatus
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);
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///
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/// If we found it, then we are done
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///
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if (!EFI_ERROR (Status)) {
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break;
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}
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}
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///
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/// Our exit status is determined by the success of the previous operations
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/// If the protocol was found, Instance already points to it.
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///
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///
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/// Free any allocated buffers
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///
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FreePool (HandleBuffer);
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///
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/// Sanity check that we found our data file
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///
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ASSERT (FwVol);
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///
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/// Locate ACPI tables
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///
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Status = gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, (VOID **) &AcpiTable);
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///
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/// Read tables from the storage file.
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///
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if (FwVol == NULL) {
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ASSERT_EFI_ERROR (EFI_NOT_FOUND);
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return EFI_NOT_FOUND;
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}
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Instance = 0;
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while (Status == EFI_SUCCESS) {
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///
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/// Read the ACPI tables
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///
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Status = FwVol->ReadSection (
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FwVol,
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&SsdtTableGuid,
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EFI_SECTION_RAW,
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Instance,
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(VOID **) &Table,
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&Size,
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&FvStatus
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);
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if (!EFI_ERROR (Status)) {
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///
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/// check and load HybridGraphics SSDT table
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///
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LoadTable = FALSE;
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TableHeader = (EFI_ACPI_DESCRIPTION_HEADER *) Table;
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if (((EFI_ACPI_DESCRIPTION_HEADER *) TableHeader)->OemTableId == Signature) {
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///
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/// This is the SSDT table that match the Signature
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///
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DEBUG ((DEBUG_INFO, "Found out SSDT Table GUID: %g\n", SsdtTableGuid));
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LoadTable = TRUE;
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}
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///
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/// Add the table
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///
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if (LoadTable) {
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TableHandle = 0;
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Status = AcpiTable->InstallAcpiTable (
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AcpiTable,
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TableHeader,
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TableHeader->Length,
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&TableHandle
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);
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}
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///
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/// Increment the instance
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///
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Instance++;
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Table = NULL;
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}
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}
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return EFI_SUCCESS;
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}
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/**
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This function gets registered as a callback to perform Dmar Igd
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@param[in] Event - A pointer to the Event that triggered the callback.
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@param[in] Context - A pointer to private data registered with the callback function.
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**/
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VOID
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EFIAPI
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SaAcpiEndOfDxeCallback (
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IN EFI_EVENT Event,
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IN VOID *Context
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)
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{
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EFI_STATUS Status;
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if (PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, IGD_BUS_NUM, IGD_DEV_NUM, IGD_FUN_NUM, PCI_VENDOR_ID_OFFSET)) != 0xFFFF) {
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Status = PostPmInitEndOfDxe ();
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if (EFI_SUCCESS != Status) {
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DEBUG ((DEBUG_WARN, "[SA] EndOfDxe GraphicsInit Error, Status = %r \n", Status));
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ASSERT_EFI_ERROR (Status);
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}
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}
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if (PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, IGD_BUS_NUM, IGD_DEV_NUM, IGD_FUN_NUM, PCI_VENDOR_ID_OFFSET)) != 0xFFFF) {
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Status = GetVBiosVbtEndOfDxe ();
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if (EFI_SUCCESS != Status) {
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DEBUG ((DEBUG_WARN, "[SA] EndOfDxe Op Region Error, Status = %r \n", Status));
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}
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Status = UpdateIgdOpRegionEndOfDxe ();
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if (EFI_SUCCESS != Status) {
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DEBUG ((DEBUG_WARN, "[SA] EndOfDxe Update Op Region Error, Status = %r \n", Status));
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}
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}
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return;
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}
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/**
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SystemAgent Acpi Initialization.
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@param[in] ImageHandle Handle for the image of this driver
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@retval EFI_SUCCESS The function completed successfully
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@retval EFI_OUT_OF_RESOURCES No enough buffer to allocate
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**/
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EFI_STATUS
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EFIAPI
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SaAcpiInit (
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IN EFI_HANDLE ImageHandle
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)
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{
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EFI_STATUS Status;
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EFI_CPUID_REGISTER CpuidRegs;
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EFI_EVENT EndOfDxeEvent;
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CPU_PCIE_HOB *CpuPcieHob;
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AsmCpuid (1, &CpuidRegs.RegEax, 0, 0, 0);
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///
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/// Get the platform setup policy.
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///
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Status = gBS->LocateProtocol (&gSaPolicyProtocolGuid, NULL, (VOID **) &mSaPolicy);
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ASSERT_EFI_ERROR (Status);
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///
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/// Install System Agent Global NVS protocol
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///
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DEBUG ((DEBUG_INFO, "Install SA GNVS protocol\n"));
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Status = (gBS->AllocatePool) (EfiACPIMemoryNVS, sizeof (SYSTEM_AGENT_NVS_AREA), (VOID **) &mSaNvsAreaProtocol.Area);
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ASSERT_EFI_ERROR (Status);
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ZeroMem ((VOID *) mSaNvsAreaProtocol.Area, sizeof (SYSTEM_AGENT_NVS_AREA));
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mSaNvsAreaProtocol.Area->XPcieCfgBaseAddress = (UINT32) (PcdGet64 (PcdSiPciExpressBaseAddress));
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mSaNvsAreaProtocol.Area->CpuIdInfo = CpuidRegs.RegEax;
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///
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/// Get CpuPcieHob HOB
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///
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CpuPcieHob = NULL;
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CpuPcieHob = (CPU_PCIE_HOB *) GetFirstGuidHob (&gCpuPcieHobGuid);
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if (CpuPcieHob == NULL) {
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DEBUG((DEBUG_ERROR, "CpuPcieHob not found\n"));
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// @todo: Will add it back once it will get add into NVS library since currently it is failing for JSL
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//ASSERT(CpuPcieHob != NULL);
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//return EFI_NOT_FOUND;
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} else {
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mSaNvsAreaProtocol.Area->SlotSelection = CpuPcieHob->SlotSelection;
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DEBUG((DEBUG_INFO, "RpEnabledMask == %x\n", CpuPcieHob->RpEnabledMask));
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if (CpuPcieHob->RpEnabledMask == 0) {
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DEBUG ((DEBUG_ERROR, "All CPU PCIe root ports are disabled!!\n"));
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} else {
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if (CpuPcieHob->RpEnabledMask & BIT0) {
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mSaNvsAreaProtocol.Area->CpuPcieRp0Enable = 1;
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}
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if (CpuPcieHob->RpEnabledMask & BIT1) {
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mSaNvsAreaProtocol.Area->CpuPcieRp1Enable = 1;
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}
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if (CpuPcieHob->RpEnabledMask & BIT2) {
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mSaNvsAreaProtocol.Area->CpuPcieRp2Enable = 1;
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}
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if (CpuPcieHob->RpEnabledMask & BIT3) {
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mSaNvsAreaProtocol.Area->CpuPcieRp3Enable = 1;
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}
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}
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mSaNvsAreaProtocol.Area->MaxPegPortNumber = GetMaxCpuPciePortNum ();
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}
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mSaNvsAreaProtocol.Area->SimicsEnvironment = 0;
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Status = gBS->InstallMultipleProtocolInterfaces (
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&ImageHandle,
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&gSaNvsAreaProtocolGuid,
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&mSaNvsAreaProtocol,
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NULL
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);
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ASSERT_EFI_ERROR (Status);
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///
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/// GtPostInit Initialization
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///
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DEBUG ((DEBUG_INFO, "Initializing GT ACPI tables\n"));
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GraphicsInit (ImageHandle, mSaPolicy);
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///
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/// Audio (dHDA) Initialization
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///
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///
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/// Vtd Initialization
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///
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DEBUG ((DEBUG_INFO, "Initializing VT-d ACPI tables\n"));
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VtdInit (mSaPolicy);
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///
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/// IgdOpRegion Install Initialization
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///
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DEBUG ((DEBUG_INFO, "Initializing IGD OpRegion\n"));
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IgdOpRegionInit ();
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///
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/// Register an end of DXE event for SA ACPI to do tasks before invoking any UEFI drivers,
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/// applications, or connecting consoles,...
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///
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Status = gBS->CreateEventEx (
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EVT_NOTIFY_SIGNAL,
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TPL_CALLBACK,
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SaAcpiEndOfDxeCallback,
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NULL,
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&gEfiEndOfDxeEventGroupGuid,
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&EndOfDxeEvent
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);
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///
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/// Install System Agent Global NVS ACPI table
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///
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Status = InstallSsdtAcpiTable (gSaSsdtAcpiTableStorageGuid, SIGNATURE_64 ('S', 'a', 'S', 's', 'd', 't', ' ', 0));
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ASSERT_EFI_ERROR (Status);
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///
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/// Update CPU PCIE RP NVS AREA
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///
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UpdateCpuPcieNVS();
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///
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/// Install Intel Graphics SSDT
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///
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Status = InstallSsdtAcpiTable (gGraphicsAcpiTableStorageGuid, SIGNATURE_64 ('I','g','f','x','S','s','d','t'));
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ASSERT_EFI_ERROR (Status);
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///
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/// Install IPU SSDT if IPU is present.
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///
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if (PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, IPU_BUS_NUM, IPU_DEV_NUM, IPU_FUN_NUM, 0)) != V_SA_DEVICE_ID_INVALID) {
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Status = InstallSsdtAcpiTable (gIpuAcpiTableStorageGuid, SIGNATURE_64 ('I','p','u','S','s','d','t',0));
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ASSERT_EFI_ERROR (Status);
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}
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return EFI_SUCCESS;
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}
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