/** @file
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This file provide services for DXE phase policy default initialization
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Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "DxeSaPolicyLibrary.h"
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#include <Library/DxeGraphicsPolicyLib.h>
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#include <Library/DxeVtdPolicyLib.h>
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#include <Register/SaRegsHostBridge.h>
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extern EFI_GUID gMemoryDxeConfigGuid;
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extern EFI_GUID gPcieDxeConfigGuid;
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/**
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This function prints the SA DXE phase policy.
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@param[in] SaPolicy - SA DXE Policy protocol
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**/
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VOID
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SaPrintPolicyProtocol (
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IN SA_POLICY_PROTOCOL *SaPolicy
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)
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{
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EFI_STATUS Status;
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PCIE_DXE_CONFIG *PcieDxeConfig;
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MEMORY_DXE_CONFIG *MemoryDxeConfig;
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//
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// Get requisite IP Config Blocks which needs to be used here
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//
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Status = GetConfigBlock ((VOID *) SaPolicy, &gPcieDxeConfigGuid, (VOID *)&PcieDxeConfig);
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ASSERT_EFI_ERROR (Status);
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Status = GetConfigBlock ((VOID *) SaPolicy, &gMemoryDxeConfigGuid, (VOID *)&MemoryDxeConfig);
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ASSERT_EFI_ERROR (Status);
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DEBUG_CODE_BEGIN ();
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INTN i;
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DEBUG ((DEBUG_INFO, "\n------------------------ SA Policy (DXE) print BEGIN -----------------\n"));
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DEBUG ((DEBUG_INFO, "Revision : %x\n", SaPolicy->TableHeader.Header.Revision));
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ASSERT (SaPolicy->TableHeader.Header.Revision == SA_POLICY_PROTOCOL_REVISION);
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DEBUG ((DEBUG_INFO, "------------------------ SA_MEMORY_CONFIGURATION -----------------\n"));
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DEBUG ((DEBUG_INFO, " SpdAddressTable[%d] :", 4));
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for (i = 0; i < 4; i++) {
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DEBUG ((DEBUG_INFO, " %x", MemoryDxeConfig->SpdAddressTable[i]));
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}
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DEBUG ((DEBUG_INFO, "\n"));
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DEBUG ((DEBUG_INFO, " ChannelASlotMap : %x\n", MemoryDxeConfig->ChannelASlotMap));
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DEBUG ((DEBUG_INFO, " ChannelBSlotMap : %x\n", MemoryDxeConfig->ChannelBSlotMap));
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DEBUG ((DEBUG_INFO, " MrcTimeMeasure : %x\n", MemoryDxeConfig->MrcTimeMeasure));
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DEBUG ((DEBUG_INFO, " MrcFastBoot : %x\n", MemoryDxeConfig->MrcFastBoot));
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DEBUG ((DEBUG_INFO, "------------------------ CPU_PCIE_CONFIGURATION -----------------\n"));
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DEBUG ((DEBUG_INFO, " PegAspm[%d] :", SA_PEG_MAX_FUN));
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for (i = 0; i < SA_PEG_MAX_FUN; i++) {
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DEBUG ((DEBUG_INFO, " %x", PcieDxeConfig->PegAspm[i]));
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}
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DEBUG ((DEBUG_INFO, "\n"));
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DEBUG ((DEBUG_INFO, " PegRootPortHPE[%d] :", SA_PEG_MAX_FUN));
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for (i = 0; i < SA_PEG_MAX_FUN; i++) {
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DEBUG ((DEBUG_INFO, " %x", PcieDxeConfig->PegRootPortHPE[i]));
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}
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DEBUG ((DEBUG_INFO, "\n"));
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DEBUG ((DEBUG_INFO, "\n------------------------ SA Policy (DXE) print END -----------------\n"));
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DEBUG_CODE_END ();
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return;
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}
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/**
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Load DXE Config block default for PCIe
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@param[in] ConfigBlockPointer Pointer to config block
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**/
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VOID
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LoadPcieDxeDefault (
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IN VOID *ConfigBlockPointer
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)
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{
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UINT8 Index;
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PCIE_DXE_CONFIG *PcieDxeConfig;
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PcieDxeConfig = ConfigBlockPointer;
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DEBUG ((DEBUG_INFO, "PcieDxeConfig->Header.GuidHob.Name = %g\n", &PcieDxeConfig->Header.GuidHob.Name));
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DEBUG ((DEBUG_INFO, "PcieDxeConfig->Header.GuidHob.Header.HobLength = 0x%x\n", PcieDxeConfig->Header.GuidHob.Header.HobLength));
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///
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/// Initialize the PCIE Configuration
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/// PEG ASPM per port configuration. 4 PEG controllers i.e. 0,1,2,3
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///
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for (Index = 0; Index < SA_PEG_MAX_FUN; Index++) {
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PcieDxeConfig->PegAspm[Index] = CpuPcieAspmAutoConfig;
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}
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for (Index = 0; Index < SA_PEG_MAX_FUN; Index++) {
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PcieDxeConfig->PegPwrOpt[Index].LtrEnable = 1;
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PcieDxeConfig->PegPwrOpt[Index].LtrMaxSnoopLatency = V_SA_LTR_MAX_SNOOP_LATENCY_VALUE;
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PcieDxeConfig->PegPwrOpt[Index].LtrMaxNoSnoopLatency = V_SA_LTR_MAX_NON_SNOOP_LATENCY_VALUE;
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PcieDxeConfig->PegPwrOpt[Index].ObffEnable = 1;
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}
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}
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/**
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Load DXE Config block default
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@param[in] ConfigBlockPointer Pointer to config block
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**/
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VOID
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LoadMemoryDxeDefault (
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IN VOID *ConfigBlockPointer
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)
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{
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MEMORY_DXE_CONFIG *MemoryDxeConfig;
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MemoryDxeConfig = ConfigBlockPointer;
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DEBUG ((DEBUG_INFO, "MemoryDxeConfig->Header.GuidHob.Name = %g\n", &MemoryDxeConfig->Header.GuidHob.Name));
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DEBUG ((DEBUG_INFO, "MemoryDxeConfig->Header.GuidHob.Header.HobLength = 0x%x\n", MemoryDxeConfig->Header.GuidHob.Header.HobLength));
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///
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/// Initialize the Memory Configuration
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///
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///
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/// DIMM SMBus addresses info
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/// Refer to the SpdAddressTable[] mapping rule in DxeSaPolicyLibrary.h
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///
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MemoryDxeConfig->SpdAddressTable = AllocateZeroPool (sizeof (UINT8) * 4);
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ASSERT (MemoryDxeConfig->SpdAddressTable != NULL);
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if (MemoryDxeConfig->SpdAddressTable != NULL) {
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MemoryDxeConfig->SpdAddressTable[0] = DIMM_SMB_SPD_P0C0D0;
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MemoryDxeConfig->SpdAddressTable[1] = DIMM_SMB_SPD_P0C0D1;
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MemoryDxeConfig->SpdAddressTable[2] = DIMM_SMB_SPD_P0C1D0;
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MemoryDxeConfig->SpdAddressTable[3] = DIMM_SMB_SPD_P0C1D1;
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}
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MemoryDxeConfig->ChannelASlotMap = 0x01;
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MemoryDxeConfig->ChannelBSlotMap = 0x01;
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}
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GLOBAL_REMOVE_IF_UNREFERENCED COMPONENT_BLOCK_ENTRY mSaDxeIpBlocks [] = {
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{&gPcieDxeConfigGuid, sizeof (PCIE_DXE_CONFIG), PCIE_DXE_CONFIG_REVISION, LoadPcieDxeDefault},
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{&gMemoryDxeConfigGuid, sizeof (MEMORY_DXE_CONFIG), MEMORY_DXE_CONFIG_REVISION, LoadMemoryDxeDefault}
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};
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/**
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CreateSaDxeConfigBlocks generates the config blocks of SA DXE Policy.
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It allocates and zero out buffer, and fills in the Intel default settings.
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@param[out] SaPolicy The pointer to get SA DXE Protocol instance
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@retval EFI_SUCCESS The policy default is initialized.
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@retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
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**/
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EFI_STATUS
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EFIAPI
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CreateSaDxeConfigBlocks (
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IN OUT SA_POLICY_PROTOCOL **SaPolicy
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)
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{
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UINT16 TotalBlockSize;
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EFI_STATUS Status;
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SA_POLICY_PROTOCOL *SaInitPolicy;
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UINT16 RequiredSize;
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DEBUG ((DEBUG_INFO, "SA Create Dxe Config Blocks\n"));
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SaInitPolicy = NULL;
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TotalBlockSize = GetComponentConfigBlockTotalSize (&mSaDxeIpBlocks[0], sizeof (mSaDxeIpBlocks) / sizeof (COMPONENT_BLOCK_ENTRY));
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TotalBlockSize += VtdGetConfigBlockTotalSizeDxe ();
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TotalBlockSize += GraphicsGetConfigBlockTotalSizeDxe ();
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DEBUG ((DEBUG_INFO, "TotalBlockSize = 0x%x\n", TotalBlockSize));
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RequiredSize = sizeof (CONFIG_BLOCK_TABLE_HEADER) + TotalBlockSize;
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Status = CreateConfigBlockTable (RequiredSize, (VOID *) &SaInitPolicy);
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ASSERT_EFI_ERROR (Status);
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//
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// Initialize Policy Revision
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//
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SaInitPolicy->TableHeader.Header.Revision = SA_POLICY_PROTOCOL_REVISION;
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//
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// Add config blocks.
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//
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Status = AddComponentConfigBlocks ((VOID *) SaInitPolicy, &mSaDxeIpBlocks[0], sizeof (mSaDxeIpBlocks) / sizeof (COMPONENT_BLOCK_ENTRY));
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ASSERT_EFI_ERROR (Status);
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// Vtd
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Status = VtdAddConfigBlocksDxe((VOID *) SaInitPolicy);
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ASSERT_EFI_ERROR (Status);
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// Gfx
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Status = GraphicsAddConfigBlocksDxe ((VOID *) SaInitPolicy);
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ASSERT_EFI_ERROR (Status);
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//
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// Assignment for returning SaInitPolicy config block base address
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//
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*SaPolicy = SaInitPolicy;
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return Status;
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}
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/**
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SaInstallPolicyProtocol installs SA Policy.
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While installed, RC assumes the Policy is ready and finalized. So please update and override
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any setting before calling this function.
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@param[in] ImageHandle Image handle of this driver.
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@param[in] SaPolicy The pointer to SA Policy Protocol instance
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@retval EFI_SUCCESS The policy is installed.
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@retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
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**/
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EFI_STATUS
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EFIAPI
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SaInstallPolicyProtocol (
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IN EFI_HANDLE ImageHandle,
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IN SA_POLICY_PROTOCOL *SaPolicy
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)
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{
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EFI_STATUS Status;
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///
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/// Print SA DXE Policy
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///
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SaPrintPolicyProtocol (SaPolicy);
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GraphicsDxePolicyPrint (SaPolicy);
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VtdPrintPolicyDxe (SaPolicy);
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///
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/// Install protocol to to allow access to this Policy.
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///
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Status = gBS->InstallMultipleProtocolInterfaces (
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&ImageHandle,
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&gSaPolicyProtocolGuid,
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SaPolicy,
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NULL
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);
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ASSERT_EFI_ERROR (Status);
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return Status;
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}
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