/** @file
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This file defines the SA Iotrap SMI Protocol to provide the
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I/O address for registered Iotrap SMI.
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Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _SA_IOTRAP_SMI_PROTOCOL_H_
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#define _SA_IOTRAP_SMI_PROTOCOL_H_
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//
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// Extern the GUID for protocol users.
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//
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extern EFI_GUID gSaIotrapSmiProtocolGuid;
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#define SA_IOTRAP_SMI_PROTOCOL_REVISION_1 1
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//
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// SA IO Trap SMI Protocol definition (Private protocol for RC internal use only)
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//
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typedef struct {
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/*
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Protocol revision number
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Any backwards compatible changes to this protocol will result in an update in the revision number
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Major changes will require publication of a new protocol
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<b>Revision 1</b>:
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- First version
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*/
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UINT8 Revision;
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UINT16 SaIotrapSmiAddress;
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} SA_IOTRAP_SMI_PROTOCOL;
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///
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/// Pcie Trap valid types
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///
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typedef enum {
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CpuPciePmTrap,
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CpuPcieTrapTypeMaximum
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} CPU_PCIE_TRAP_TYPE;
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#endif
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