/** @file
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PCIE DXE policy definitions
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Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _PCIE_DXE_CONFIG_H_
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#define _PCIE_DXE_CONFIG_H_
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#include "CpuPcieInfo.h"
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#pragma pack(push, 1)
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#define PCIE_DXE_CONFIG_REVISION 2
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typedef struct {
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UINT16 VendorId; ///< Offset 0 PCI Config space offset 0
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UINT16 DeviceId; ///< Offset 2 PCI Config space offset 2
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/**
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Offset 4:
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SnoopLatency bit definition
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Note: All Reserved bits must be set to 0
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BIT[15] - When set to 1b, indicates that the values in bits 9:0 are valid
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When clear values in bits 9:0 will be ignored
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BIT[14] - Should be set to 0b
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BIT[13] - Reserved
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BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits
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000b - 1 ns
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001b - 32 ns
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010b - 1024 ns
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011b - 32,768 ns
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100b - 1,048,576 ns
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101b - 33,554,432 ns
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110b - Reserved
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111b - Reserved
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BITS[9:0] - Snoop Latency Value. The value in these bits will be multiplied with
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the scale in bits 12:10
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**/
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UINT16 SnoopLatency;
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/**
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Offset 6:
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NonSnoopLatency bit definition
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Note: All Reserved bits must be set to 0
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BIT[15] - When set to 1b, indicates that the values in bits 9:0 are valid
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When clear values in bits 9:0 will be ignored
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BIT[14] - Should be set to 0b
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BIT[13] - Reserved
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BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits
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000b - 1 ns
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001b - 32 ns
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010b - 1024 ns
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011b - 32,768 ns
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100b - 1,048,576 ns
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101b - 33,554,432 ns
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110b - Reserved
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111b - Reserved
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BITS[9:0] - Non Snoop Latency Value. The value in these bits will be multiplied with
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the scale in bits 12:10
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**/
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UINT16 NonSnoopLatency;
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UINT8 RevId; ///< Offset 8 PCI Config space offset 8; 0xFF means all steppings
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UINT8 Rsvd0[3]; ///< Offset 9
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} PCIE_LTR_DEV_INFO;
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///
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/// PCIE Power Optimizer config
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///
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typedef struct {
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UINT16 LtrMaxSnoopLatency; ///< Offset 0 LTR Maximum Snoop Latency: <b>0x0846=70us</b>
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UINT16 LtrMaxNoSnoopLatency; ///< Offset 2 LTR Maximum Non-Snoop Latency: <b>0x0846=70us</b>
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UINT8 ObffEnable; ///< Offset 4 LTR enable/disable: 0=Disable, <b>1=Enable</b>
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UINT8 LtrEnable; ///< Offset 5 LTR enable/disable: 0=Disable, <b>1=Enable</b>
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UINT8 Rsvd0[2]; ///< Offset 6 Reserved
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} CPU_PCIE_PWR_OPT;
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/**
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The PCI Express Configuration info includes PCI Resources Range Base and Limits and the control
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for PEG ASPM.
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The data elements should be initialized by a Platform Module.\n
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@note <b>Optional.</b> These policies will be ignored if there is no PEG port present on board.
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<b>Revision 1</b>:
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- Initial version.
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<b>Revision 2</b>:
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- Adding PEG RTD3 Support Setup Variable
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<b>Revision 3</b>:
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- Adding CPU PCIE RTD3 Support Setup Variable
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- Deprecating PEG RTD3 Support Setup Variable
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<b>Revision 4</b>:
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- Deprecating CPU PCIE RTD3 Support Setup Variable
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**/
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typedef struct {
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CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
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/**
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Offset 28: This field is used to describe the ASPM control for PEG Ports\n
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0=ASPM Disabled, 1=ASPM L0s Enabled, 2=ASPM L1 Enabled, 3=ASPM L0sL1 Enabled, <b>4=ASPM AUTO</b>
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**/
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UINT8 PegAspm[SA_PEG_MAX_FUN];
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/**
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Offset 32: PCIe Hot Plug Enable/Disable. It has 2 policies.
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- <b>Disabled (0x0)</b> : No hotplug.
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- Enabled (0x1) : Bios assist hotplug.
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**/
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UINT8 PegRootPortHPE[SA_PEG_MAX_FUN];
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CPU_PCIE_PWR_OPT PegPwrOpt[SA_PEG_MAX_FUN]; ///< Offset 36: This field is used to describe the PCIe LTR/OBFF relevant settings
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UINT32 PegRtd3; /// Deprecated Policy
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UINT8 CpuPcieRtd3; ///< Enable/Disable RTD3 Support for CPU PCIE. 0=Disable and 1=Enable (default) // Deprecated Policy
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UINT8 Rsvd3[3];
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} PCIE_DXE_CONFIG;
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#pragma pack(pop)
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#endif // _PCIE_DXE_CONFIG_H_
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