/** @file
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Gbe Sx handler implementation.
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Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Library/TimerLib.h>
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#include "PchInitSmm.h"
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#include <Library/PmcPrivateLib.h>
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#include <Library/GbeMdiLib.h>
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#include <Library/GbeLib.h>
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#include <Register/PchRegs.h>
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#include <Register/GbeRegs.h>
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#include <Library/PchPciBdfLib.h>
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/**
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Configure WOL during Sx entry.
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@param [in] GbeBar GbE MMIO space
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**/
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VOID
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GbeWolWorkaround (
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IN UINT32 GbeBar
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)
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{
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UINT32 RAL0;
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UINT32 RAH0;
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UINT16 WUC;
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EFI_STATUS Status;
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UINT16 Data16;
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//
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// 1. Set page to 769 Port Control Registers
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// 2. Wait 4 mSec
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//
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Status = GbeMdiSetPage (GbeBar, PHY_MDI_PAGE_769_PORT_CONTROL_REGISTERS);
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if (EFI_ERROR (Status)) return;
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//
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// 3. Set registry to 17 Port General Configuration
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// 4. Copy all settings from Port General Configuration
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//
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Status = GbeMdiRead (GbeBar, B_PHY_MDI_PHY_ADDRESS_01, MDI_REG_SHIFT (R_PHY_MDI_PAGE_769_REGISETER_17_PGC), &Data16);
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if (EFI_ERROR (Status)) return;
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//
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// 5. Modify BIT 4 and BIT 2 to disable host wake up and set MACPD
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//
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Status = GbeMdiWrite (GbeBar, B_PHY_MDI_PHY_ADDRESS_01, MDI_REG_SHIFT (R_PHY_MDI_PAGE_769_REGISETER_17_PGC), (Data16 | B_PHY_MDI_PAGE_769_REGISETER_17_PGC_MACPD_ENABLE) & (~B_PHY_MDI_PAGE_769_REGISETER_17_PGC_HOST_WAKE_UP));
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if (EFI_ERROR (Status)) return;
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//
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// 6. Read Receive Address Low and Receive Address High from MMIO
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//
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RAL0 = MmioRead32 (GbeBar + R_GBE_MEM_CSR_RAL);
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RAH0 = MmioRead32 (GbeBar + R_GBE_MEM_CSR_RAH);
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//
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// 7. Set page to 800 Wake Up Registers
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// 8. Wait 4 mSec
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//
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Status = GbeMdiSetPage (GbeBar, PHY_MDI_PAGE_800_WAKE_UP_REGISTERS);
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if (EFI_ERROR (Status)) return;
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//
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// 9. Set registry to 16 Receive Address Low 1/2
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//
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Status = GbeMdiSetRegister (GbeBar, R_PHY_MDI_PAGE_800_REGISETER_16_RAL0);
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if (EFI_ERROR (Status)) return;
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//
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// 10. Program first 16 bits [0:15] out of 48 in Receive Address Low 1/2
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//
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Status = GbeMdiWrite (GbeBar, B_PHY_MDI_PHY_ADDRESS_01, R_PHY_MDI_PHY_REG_DATA_READ_WRITE, (RAL0 & 0xFFFF));
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if (EFI_ERROR (Status)) return;
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//
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// 11. Set registry to 17 Receive Address Low 2/2
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//
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Status = GbeMdiSetRegister (GbeBar, R_PHY_MDI_PAGE_800_REGISETER_17_RAL1);
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if (EFI_ERROR (Status)) return;
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//
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// 12. Program second 16 bits [16:31] out of 48 in Receive Address Low 2/2
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//
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Status = GbeMdiWrite (GbeBar, B_PHY_MDI_PHY_ADDRESS_01, R_PHY_MDI_PHY_REG_DATA_READ_WRITE, (RAL0 >> 16));
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if (EFI_ERROR (Status)) return;
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//
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// 13. Set registry to 18 Receive Address High 1/2
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//
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Status = GbeMdiSetRegister (GbeBar, R_PHY_MDI_PAGE_800_REGISETER_18_RAH0);
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if (EFI_ERROR (Status)) return;
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//
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// 14. Program last 16 bits [32:47] out of 48
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//
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Status = GbeMdiWrite (GbeBar, B_PHY_MDI_PHY_ADDRESS_01, R_PHY_MDI_PHY_REG_DATA_READ_WRITE, (RAH0 & B_GBE_MEM_CSR_RAH_RAH));
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if (EFI_ERROR (Status)) return;
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//
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// 15. Set registry to 19 Receive Address High 2/2
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//
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Status = GbeMdiSetRegister (GbeBar, R_PHY_MDI_PAGE_800_REGISETER_19_RAH1);
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if (EFI_ERROR (Status)) return;
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//
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// 16. Set Address Valid
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//
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Status = GbeMdiWrite (GbeBar, B_PHY_MDI_PHY_ADDRESS_01, R_PHY_MDI_PHY_REG_DATA_READ_WRITE, B_PHY_MDI_PAGE_800_REGISETER_19_RAH1_ADDRESS_VALID);
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if (EFI_ERROR (Status)) return;
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//
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// 17. Set Wake Up Control Register 1
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//
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Status = GbeMdiSetRegister (GbeBar, R_PHY_MDI_PAGE_800_REGISETER_1_WUC);
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if (EFI_ERROR (Status)) return;
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//
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// 18. Copy WakeUp Control from MAC MMIO
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//
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WUC = (UINT16) MmioRead32 (GbeBar + R_GBE_MEM_CSR_WUC);
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//
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// 19. Store WakeUp Contorl into LCD
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// Modify APME bit to enable APM wake up
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//
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Status = GbeMdiWrite (GbeBar, B_PHY_MDI_PHY_ADDRESS_01, R_PHY_MDI_PHY_REG_DATA_READ_WRITE, (WUC & 0xFFFF));
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if (EFI_ERROR (Status)) return;
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//
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// 20. Set page to 803 Host Wol Packet
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// 21. Wait 4 mSec
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//
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Status = GbeMdiSetPage (GbeBar, PHY_MDI_PAGE_803_HOST_WOL_PACKET);
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if (EFI_ERROR (Status)) return;
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//
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// 22. Set registry to 66 Host WoL Packet Clear
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//
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Status = GbeMdiSetRegister (GbeBar, R_PHY_MDI_PAGE_803_REGISETER_66_HWPC);
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if (EFI_ERROR (Status)) return;
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//
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// 23. Clear WOL Packet
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//
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Status = GbeMdiWrite (GbeBar, B_PHY_MDI_PHY_ADDRESS_01, R_PHY_MDI_PHY_REG_DATA_READ_WRITE, 0);
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if (EFI_ERROR (Status)) return;
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//
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// 24. Set page to 769 Port Control Registers
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// 25. Wait 4 mSec
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//
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Status = GbeMdiSetPage (GbeBar, PHY_MDI_PAGE_769_PORT_CONTROL_REGISTERS);
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if (EFI_ERROR (Status)) return;
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//
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// 26. Set registry to 17 Port General Configuration
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//
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Status = GbeMdiSetRegister (GbeBar, R_PHY_MDI_PAGE_769_REGISETER_17_PGC);
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if (EFI_ERROR (Status)) return;
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//
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// 27. Copy all settings from Port General Configuration
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//
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Status = GbeMdiRead (GbeBar, B_PHY_MDI_PHY_ADDRESS_01, MDI_REG_SHIFT (R_PHY_MDI_PAGE_769_REGISETER_17_PGC), &Data16);
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if (EFI_ERROR (Status)) return;
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//
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// 28. Modify BIT 4 and BIT 2 to enable host wake up and clear MACPD
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//
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Status = GbeMdiWrite (GbeBar, B_PHY_MDI_PHY_ADDRESS_01, MDI_REG_SHIFT (R_PHY_MDI_PAGE_769_REGISETER_17_PGC), (Data16 | B_PHY_MDI_PAGE_769_REGISETER_17_PGC_HOST_WAKE_UP) & (~B_PHY_MDI_PAGE_769_REGISETER_17_PGC_MACPD_ENABLE));
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if (EFI_ERROR (Status)) return;
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}
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/**
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Additional Internal GbE Controller special cases WOL Support.
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System BIOS is required perform additional steps upon S0 to S3,4,5 transition
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when ME is off and GbE device in D0. This is needed to enable LAN wake
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in particular when platform is shut-down from EFI.
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**/
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VOID
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GbeSxWorkaround (
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VOID
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)
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{
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UINT64 LanRegBase;
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UINT32 GbeBar;
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EFI_STATUS Status;
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LanRegBase = GbePciCfgBase ();
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if (PciSegmentRead16 (LanRegBase + PCI_VENDOR_ID_OFFSET) == 0xFFFF) {
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return;
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}
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//
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// Check if GbE device is in D0
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//
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if ((PciSegmentRead16 (LanRegBase + R_GBE_CFG_PMCS) & B_GBE_CFG_PMCS_PS) != V_GBE_CFG_PMCS_PS0) {
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return;
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}
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ASSERT (mResvMmioSize >= (1 << N_GBE_CFG_MBARA_ALIGN));
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GbeBar = (UINT32) mResvMmioBaseAddr;
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if (GbeBar == 0) {
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ASSERT (FALSE);
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return;
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}
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//
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// Enable MMIO decode using reserved range.
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//
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PciSegmentAnd16 (LanRegBase + PCI_COMMAND_OFFSET, (UINT16) ~EFI_PCI_COMMAND_MEMORY_SPACE);
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PciSegmentWrite32 (LanRegBase + R_GBE_CFG_MBARA, GbeBar);
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PciSegmentOr16 (LanRegBase + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_MEMORY_SPACE);
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//
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// If MBARA offset 5800h [0] = 1b then proceed with the w/a
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//
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if (MmioRead32 (GbeBar + R_GBE_MEM_CSR_WUC) & B_GBE_MEM_CSR_WUC_APME) {
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Status = GbeMdiAcquireMdio (GbeBar);
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ASSERT_EFI_ERROR (Status);
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if (!EFI_ERROR (Status)) {
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GbeWolWorkaround (GbeBar);
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GbeMdiReleaseMdio (GbeBar);
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}
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}
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//
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// Disable MMIO decode.
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//
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PciSegmentAnd16 (LanRegBase + PCI_COMMAND_OFFSET, (UINT16) ~EFI_PCI_COMMAND_MEMORY_SPACE);
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PciSegmentWrite32 (LanRegBase + R_GBE_CFG_MBARA, 0);
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}
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/**
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Enable platform wake from LAN when in DeepSx if platform supports it.
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Called upon Sx entry.
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**/
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VOID
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GbeConfigureDeepSxWake (
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VOID
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)
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{
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if (PmcIsLanDeepSxWakeEnabled ()) {
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IoOr32 ((UINTN) (mAcpiBaseAddr + R_ACPI_IO_GPE0_EN_127_96), (UINT32) B_ACPI_IO_GPE0_EN_127_96_LAN_WAKE);
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}
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}
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/**
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GbE Sx entry handler
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**/
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VOID
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PchLanSxCallback (
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VOID
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)
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{
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if (IsGbeEnabled ()) {
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GbeSxWorkaround ();
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GbeConfigureDeepSxWake ();
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}
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}
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