/** @file
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This is the Common driver that initializes the Intel PCH.
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Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Library/DebugLib.h>
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#include <Library/IoLib.h>
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#include <Library/PciSegmentLib.h>
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#include <Library/TimerLib.h>
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#include <Library/S3BootScriptLib.h>
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#include <Library/HobLib.h>
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#include "PchInit.h"
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#include <PchPolicyCommon.h>
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#include <Library/SpiCommonLib.h>
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#include <Library/PmcPrivateLib.h>
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#include <Library/PchDmiLib.h>
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#include <Library/SiScheduleResetLib.h>
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#include <Library/PchCycleDecodingLib.h>
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#include <Library/PchPcrLib.h>
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#include <IndustryStandard/Pci30.h>
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#include <Library/SpiAccessPrivateLib.h>
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#include <Register/PchRegs.h>
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#include <Register/PchPcrRegs.h>
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#include <Register/PchRegsLpc.h>
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#include <Register/SpiRegs.h>
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#include <Register/PchRegsPsth.h>
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#include <Register/PmcRegs.h>
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#include <Register/HdaRegs.h>
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#include <Library/GpioCheckConflictLib.h>
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#include <Library/PchPciBdfLib.h>
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#include <Library/PchInfoLib.h>
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//
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// Module variables
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//
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GLOBAL_REMOVE_IF_UNREFERENCED PCH_CONFIG_HOB *mPchConfigHob;
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//
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// EFI_EVENT
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//
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GLOBAL_REMOVE_IF_UNREFERENCED EFI_EVENT mHeciEvent;
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/**
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Common PchInit Module Entry Point
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**/
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VOID
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PchInitEntryPointCommon (
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VOID
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)
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{
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EFI_PEI_HOB_POINTERS HobPtr;
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DEBUG ((DEBUG_INFO, "PchInitEntryPointCommon() Start\n"));
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//
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// Get PCH Config HOB.
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//
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HobPtr.Guid = GetFirstGuidHob (&gPchConfigHobGuid);
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ASSERT (HobPtr.Guid != NULL);
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mPchConfigHob = (PCH_CONFIG_HOB *) GET_GUID_HOB_DATA (HobPtr.Guid);
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DEBUG ((DEBUG_INFO, "PchInitEntryPointCommon() End\n"));
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return;
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}
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/**
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Lock SPI register before boot
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**/
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VOID
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LockSpiConfiguration (
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VOID
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)
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{
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UINTN Index;
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UINT16 Data16;
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UINT16 Data16And;
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UINT16 Data16Or;
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UINT32 Data32;
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UINT32 DlockValue;
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UINT64 PciSpiRegBase;
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UINT32 PchSpiBar0;
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UINT32 Timer;
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PciSpiRegBase = SpiPciCfgBase ();
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//
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// Check for SPI controller presence before programming
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//
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if (PciSegmentRead16 (PciSpiRegBase + PCI_VENDOR_ID_OFFSET) == 0xFFFF) {
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return;
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}
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//
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// Make sure SPI BAR0 has fixed address before writing to boot script.
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// The same base address is set in PEI and will be used during resume.
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//
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PchSpiBar0 = PCH_SPI_BASE_ADDRESS;
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PciSegmentAnd8 (PciSpiRegBase + PCI_COMMAND_OFFSET, (UINT8) ~EFI_PCI_COMMAND_MEMORY_SPACE);
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PciSegmentWrite32 (PciSpiRegBase + R_SPI_CFG_BAR0, PchSpiBar0);
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PciSegmentOr8 (PciSpiRegBase + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_MEMORY_SPACE);
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//
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// Locking for security reasons only if Extended BIOS Range Decode is supported
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//
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if (IsExtendedBiosRangeDecodeSupported ()) {
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//
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// Before setting FLOCKDN lock Extended BIOS Range configuration
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// All configuration of this feature shall be done already at this moment
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//
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PciSegmentOr32 (PciSpiRegBase + R_SPI_CFG_BC, BIT28);
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S3BootScriptSavePciCfgWrite (
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S3BootScriptWidthUint32,
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(UINTN) PciSpiRegBase + R_SPI_CFG_BC,
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1,
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(VOID *) (UINTN) (PciSpiRegBase + R_SPI_CFG_BC)
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);
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}
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//
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// Program the Flash Protection Range Register based on policy
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//
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DlockValue = MmioRead32 (PchSpiBar0 + R_SPI_MEM_DLOCK);
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for (Index = 0; Index < PCH_FLASH_PROTECTED_RANGES; ++Index) {
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if ((mPchConfigHob->ProtectRange[Index].WriteProtectionEnable ||
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mPchConfigHob->ProtectRange[Index].ReadProtectionEnable) != TRUE) {
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continue;
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}
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//
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// Proceed to program the register after ensure it is enabled
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//
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Data32 = 0;
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Data32 |= (mPchConfigHob->ProtectRange[Index].WriteProtectionEnable == TRUE) ? B_SPI_MEM_PRX_WPE : 0;
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Data32 |= (mPchConfigHob->ProtectRange[Index].ReadProtectionEnable == TRUE) ? B_SPI_MEM_PRX_RPE : 0;
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Data32 |= ((UINT32) mPchConfigHob->ProtectRange[Index].ProtectedRangeLimit << N_SPI_MEM_PRX_PRL) & B_SPI_MEM_PRX_PRL_MASK;
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Data32 |= ((UINT32) mPchConfigHob->ProtectRange[Index].ProtectedRangeBase << N_SPI_MEM_PRX_PRB) & B_SPI_MEM_PRX_PRB_MASK;
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DEBUG ((DEBUG_INFO, "Protected range %d: 0x%08x \n", Index, Data32));
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DlockValue |= (UINT32) (B_SPI_MEM_DLOCK_PR0LOCKDN << Index);
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MmioWrite32 ((UINTN) (PchSpiBar0 + (R_SPI_MEM_PR0 + (Index * S_SPI_MEM_PRX))), Data32);
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S3BootScriptSaveMemWrite (
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S3BootScriptWidthUint32,
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(UINTN) (PchSpiBar0 + (R_SPI_MEM_PR0 + (Index * S_SPI_MEM_PRX))),
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1,
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(VOID *) (UINTN) (PchSpiBar0 + (R_SPI_MEM_PR0 + (Index * S_SPI_MEM_PRX)))
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);
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}
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//
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// Program DLOCK register
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//
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MmioWrite32 ((UINTN) (PchSpiBar0 + R_SPI_MEM_DLOCK), DlockValue);
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S3BootScriptSaveMemWrite (
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S3BootScriptWidthUint32,
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(UINTN) (PchSpiBar0 + R_SPI_MEM_DLOCK),
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1,
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(VOID *) (UINTN) (PchSpiBar0 + R_SPI_MEM_DLOCK)
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);
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///
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/// PCH BIOS Spec Section 3.6 Flash Security Recommendation
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/// In PCH SPI controller the BIOS should set the Flash Configuration Lock-Down bit
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/// (SPI_BAR0 + 04[15]) at end of post. When set to 1, those Flash Program Registers
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/// that are locked down by this FLOCKDN bit cannot be written.
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/// Please refer to the EDS for which program registers are impacted.
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/// Additionally BIOS must program SPI_BAR0 + 0x04 BIT11 (WRSDIS) to disable Write Status in HW sequencing
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///
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//
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// Ensure there is no pending SPI trasaction before setting lock bits
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//
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Timer = 0;
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while (MmioRead16 (PchSpiBar0 + R_SPI_MEM_HSFSC) & B_SPI_MEM_HSFSC_SCIP) {
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if (Timer > SPI_WAIT_TIME) {
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//
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// SPI transaction is pending too long at this point, exit with error.
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//
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DEBUG ((DEBUG_ERROR, "SPI Cycle timeout\n"));
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ASSERT (FALSE);
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break;
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}
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MicroSecondDelay (SPI_WAIT_PERIOD);
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Timer += SPI_WAIT_PERIOD;
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}
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Data16And = B_SPI_MEM_HSFSC_SCIP;
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Data16 = 0;
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S3BootScriptSaveMemPoll (
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S3BootScriptWidthUint16,
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PchSpiBar0 + R_SPI_MEM_HSFSC,
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&Data16And,
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&Data16,
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SPI_WAIT_PERIOD,
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SPI_WAIT_TIME / SPI_WAIT_PERIOD
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);
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//
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// Clear any outstanding status
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//
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Data16Or = B_SPI_MEM_HSFSC_SAF_DLE
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| B_SPI_MEM_HSFSC_SAF_ERROR
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| B_SPI_MEM_HSFSC_AEL
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| B_SPI_MEM_HSFSC_FCERR
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| B_SPI_MEM_HSFSC_FDONE;
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Data16And = 0xFFFF;
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MmioAndThenOr16 (PchSpiBar0 + R_SPI_MEM_HSFSC, Data16And, Data16Or);
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S3BootScriptSaveMemReadWrite (
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S3BootScriptWidthUint16,
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PchSpiBar0 + R_SPI_MEM_HSFSC,
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&Data16Or,
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&Data16And
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);
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//
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// Set WRSDIS
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//
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Data16Or = B_SPI_MEM_HSFSC_WRSDIS;
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Data16And = 0xFFFF;
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MmioAndThenOr16 (PchSpiBar0 + R_SPI_MEM_HSFSC, Data16And, Data16Or);
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S3BootScriptSaveMemReadWrite (
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S3BootScriptWidthUint16,
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PchSpiBar0 + R_SPI_MEM_HSFSC,
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&Data16Or,
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&Data16And
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);
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//
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// Set FLOCKDN
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//
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Data16Or = B_SPI_MEM_HSFSC_FLOCKDN;
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Data16And = 0xFFFF;
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MmioAndThenOr16 (PchSpiBar0 + R_SPI_MEM_HSFSC, Data16And, Data16Or);
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S3BootScriptSaveMemReadWrite (
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S3BootScriptWidthUint16,
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PchSpiBar0 + R_SPI_MEM_HSFSC,
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&Data16Or,
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&Data16And
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);
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///
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/// SPI Flash Programming Guide Section 5.5.2 Vendor Component Lock
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/// It is strongly recommended that BIOS sets the Vendor Component Lock (VCL) bits. VCL applies
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/// the lock to both VSCC0 and VSCC1 even if VSCC0 is not used. Without the VCL bits set, it is
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/// possible to make Host/GbE VSCC register(s) changes in that can cause undesired host and
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/// integrated GbE Serial Flash functionality.
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///
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MmioOr32 ((UINTN) (PchSpiBar0 + R_SPI_MEM_SFDP0_VSCC0), B_SPI_MEM_SFDP0_VSCC0_VCL);
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S3BootScriptSaveMemWrite (
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S3BootScriptWidthUint32,
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(UINTN) (PchSpiBar0 + R_SPI_MEM_SFDP0_VSCC0),
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1,
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(VOID *) (UINTN) (PchSpiBar0 + R_SPI_MEM_SFDP0_VSCC0)
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);
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}
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/**
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Set HD Audio PME bit
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**/
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VOID
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ConfigureHdAudioPme (
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VOID
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)
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{
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UINT64 HdaPciBase;
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HdaPciBase = HdaPciCfgBase ();
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if (PciSegmentRead16 (HdaPciBase + PCI_VENDOR_ID_OFFSET) == 0xFFFF) {
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return;
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}
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///
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/// PME Enable for Audio controller
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///
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if (mPchConfigHob->HdAudio.Pme == TRUE) {
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PciSegmentOr32 (HdaPciBase + R_HDA_CFG_PCS, (UINT32) B_HDA_CFG_PCS_PMEE);
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}
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}
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/**
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Set eSPI BME bit
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**/
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VOID
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ConfigureEspiBme (
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VOID
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)
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{
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UINT64 EspiPciBase;
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EspiPciBase = EspiPciCfgBase ();
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if (PciSegmentRead16 (EspiPciBase + PCI_VENDOR_ID_OFFSET) == 0xFFFF) {
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return;
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}
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if ((PciSegmentRead32 (EspiPciBase + R_ESPI_CFG_PCBC) & B_ESPI_CFG_PCBC_ESPI_EN) == 0) {
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return;
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}
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//
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// Refer to PCH BWG.
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// To enable eSPI bus mastering BIOS must enable BME in eSPI controller
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// and also set BME bit in the respective slave devices through Configuration
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// and Capabilities register of each slave using Get_Configuration and Set_Configuration functionality.
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//
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// NOTE: The setting is also done in PEI, but might be cleared by PCI bus during PCI enumeration.
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// Therefore, reeable it after PCI enumeration done.
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//
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if (mPchConfigHob->Espi.BmeMasterSlaveEnabled == TRUE) {
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PciSegmentOr8 (EspiPciBase + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_BUS_MASTER);
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}
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}
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