/** @file
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This is the driver that initializes the Intel PCH.
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Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Library/DebugLib.h>
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#include <Library/IoLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/HobLib.h>
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#include <Library/UefiBootServicesTableLib.h>
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#include "PchInit.h"
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#include <Protocol/PchPolicy.h>
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#include <GpioDevConfig.h>
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#include <ScsConfig.h>
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#include <Library/PchInfoLib.h>
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#include <Library/GpioLib.h>
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#include <Library/GpioNativeLib.h>
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#include <Library/PchCycleDecodingLib.h>
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#include <Library/PmcLib.h>
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#include <Library/SerialIoAccessLib.h>
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#include <Library/GbeLib.h>
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#include <PchRstHob.h>
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#include <Library/PchPcieRpLib.h>
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#include <TraceHubConfig.h>
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#include <PchReservedResources.h>
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#include <Library/PciSegmentLib.h>
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#include <Register/PchRegs.h>
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#include <Library/BaseLib.h>
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#include <Register/UsbRegs.h>
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#include <Library/PcdLib.h>
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#include <IndustryStandard/Pci22.h>
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#include <PcieRegs.h>
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#include <Library/PchPcrLib.h>
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#include <Library/PchPciBdfLib.h>
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#include <PchHybridStorageHob.h>
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#include <Library/SataLib.h>
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//
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// Module variables
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//
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GLOBAL_REMOVE_IF_UNREFERENCED PCH_NVS_AREA_PROTOCOL mPchNvsAreaProtocol;
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/**
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Retrieve interrupt information about a PCH device from policy
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@param[in] UartNumber Uart number
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@retval PCH_DEVICE_INTERRUPT_CONFIG structure with device's interrupt information
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**/
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PCH_DEVICE_INTERRUPT_CONFIG
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GetUartInterrupt (
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IN UINT8 UartNumber
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)
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{
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PCH_DEVICE_INTERRUPT_CONFIG EmptyRecord;
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UINT8 DevNum;
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UINT8 FuncNum;
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UINT8 Index;
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ZeroMem (&EmptyRecord, sizeof (PCH_DEVICE_INTERRUPT_CONFIG));
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DevNum = SerialIoUartDevNumber (UartNumber);
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FuncNum = SerialIoUartFuncNumber (UartNumber);
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for (Index = 0; Index < mPchConfigHob->Interrupt.NumOfDevIntConfig; Index++) {
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if ((mPchConfigHob->Interrupt.DevIntConfig[Index].Device == DevNum) &&
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(mPchConfigHob->Interrupt.DevIntConfig[Index].Function == FuncNum)) {
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return mPchConfigHob->Interrupt.DevIntConfig[Index];
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}
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}
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return EmptyRecord;
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}
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/**
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Update ASL definitions for SerialIo devices.
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**/
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VOID
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UpdateSerialIoAcpiData (
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VOID
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)
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{
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UINT8 Index;
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for (Index = 0; Index < GetPchMaxSerialIoSpiControllersNum (); Index++) {
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mPchNvsAreaProtocol.Area->SM0[Index] = mPchConfigHob->SerialIo.SpiDeviceConfig[Index].Mode;
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mPchNvsAreaProtocol.Area->SC0[Index] = GetSerialIoSpiPciCfg (Index);
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}
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for (Index = 0; Index < GetPchMaxSerialIoI2cControllersNum (); Index++) {
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mPchNvsAreaProtocol.Area->IM0[Index] = mPchConfigHob->SerialIo.I2cDeviceConfig[Index].Mode;
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mPchNvsAreaProtocol.Area->IC0[Index] = GetSerialIoI2cPciCfg (Index);
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}
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for (Index = 0; Index < GetPchMaxSerialIoUartControllersNum (); Index++) {
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mPchNvsAreaProtocol.Area->UM0[Index] = mPchConfigHob->SerialIo.UartDeviceConfig[Index].Mode;
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mPchNvsAreaProtocol.Area->UC0[Index] = GetSerialIoUartPciCfg (Index);
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mPchNvsAreaProtocol.Area->UD0[Index] = mPchConfigHob->SerialIo.UartDeviceConfig[Index].DmaEnable;
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mPchNvsAreaProtocol.Area->UP0[Index] = mPchConfigHob->SerialIo.UartDeviceConfig[Index].PowerGating;
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mPchNvsAreaProtocol.Area->UI0[Index] = (GetUartInterrupt (Index)).Irq;
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}
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}
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#if FixedPcdGet8(PcdEmbeddedEnable) == 0x1
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/**
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Update NVS Area for Timed GPIO devices.
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**/
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VOID
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UpdateTimedGpioSetup (
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VOID
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)
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{
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mPchNvsAreaProtocol.Area->EnableTimedGpio0 = (UINT8)mPchConfigHob->Pm.EnableTimedGpio0;
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mPchNvsAreaProtocol.Area->EnableTimedGpio1 = (UINT8)mPchConfigHob->Pm.EnableTimedGpio1;
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}
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#endif
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/**
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Update NVS Area after RST PCIe Storage Remapping and before Boot
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@retval EFI_SUCCESS The function completed successfully
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@retval EFI_NOT_FOUND Couldn't fetch RstHob
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**/
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EFI_STATUS
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PchUpdateNvsAreaAfterRemapping (
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VOID
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)
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{
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UINTN Index;
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VOID *Hob;
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PCH_RST_HOB *RstHob;
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Hob = GetFirstGuidHob (&gPchRstHobGuid);
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if (Hob == NULL) {
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return EFI_NOT_FOUND;
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}
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RstHob = (PCH_RST_HOB *) GET_GUID_HOB_DATA (Hob);
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for (Index = 0; Index < PCH_MAX_RST_PCIE_STORAGE_CR; Index++) {
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mPchNvsAreaProtocol.Area->RstPcieStorageInterfaceType[Index] = RstHob->RstCrConfiguration[Index].DeviceInterface;
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mPchNvsAreaProtocol.Area->RstPcieStoragePmCapPtr[Index] = RstHob->SavedRemapedDeviceConfigSpace[Index].PmCapPtr;
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mPchNvsAreaProtocol.Area->RstPcieStoragePcieCapPtr[Index] = RstHob->SavedRemapedDeviceConfigSpace[Index].PcieCapPtr;
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mPchNvsAreaProtocol.Area->RstPcieStorageL1ssCapPtr[Index] = RstHob->SavedRemapedDeviceConfigSpace[Index].L1ssCapPtr;
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mPchNvsAreaProtocol.Area->RstPcieStorageEpL1ssControl2[Index] = RstHob->SavedRemapedDeviceConfigSpace[Index].EndpointL1ssControl2;
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mPchNvsAreaProtocol.Area->RstPcieStorageEpL1ssControl1[Index] = RstHob->SavedRemapedDeviceConfigSpace[Index].EndpointL1ssControl1;
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mPchNvsAreaProtocol.Area->RstPcieStorageLtrCapPtr[Index] = RstHob->SavedRemapedDeviceConfigSpace[Index].LtrCapPtr;
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mPchNvsAreaProtocol.Area->RstPcieStorageEpLtrData[Index] = RstHob->SavedRemapedDeviceConfigSpace[Index].EndpointLtrData;
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mPchNvsAreaProtocol.Area->RstPcieStorageEpLctlData16[Index] = RstHob->SavedRemapedDeviceConfigSpace[Index].EndpointLctlData16;
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mPchNvsAreaProtocol.Area->RstPcieStorageEpDctlData16[Index] = RstHob->SavedRemapedDeviceConfigSpace[Index].EndpointDctlData16;
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mPchNvsAreaProtocol.Area->RstPcieStorageEpDctl2Data16[Index] = RstHob->SavedRemapedDeviceConfigSpace[Index].EndpointDctl2Data16;
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mPchNvsAreaProtocol.Area->RstPcieStorageRpDctl2Data16[Index] = RstHob->SavedRemapedDeviceConfigSpace[Index].RootPortDctl2Data16;
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mPchNvsAreaProtocol.Area->RstPcieStorageUniqueTableBar[Index] = RstHob->RstCrConfiguration[Index].EndPointUniqueMsixTableBar;
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mPchNvsAreaProtocol.Area->RstPcieStorageUniqueTableBarValue[Index] = RstHob->RstCrConfiguration[Index].EndPointUniqueMsixTableBarValue;
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mPchNvsAreaProtocol.Area->RstPcieStorageUniquePbaBar[Index] = RstHob->RstCrConfiguration[Index].EndPointUniqueMsixPbaBar;
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mPchNvsAreaProtocol.Area->RstPcieStorageUniquePbaBarValue[Index] = RstHob->RstCrConfiguration[Index].EndPointUniqueMsixPbaBarValue;
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mPchNvsAreaProtocol.Area->RstPcieStorageRootPortNum[Index] = RstHob->RstCrConfiguration[Index].RootPortNum;
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}
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return EFI_SUCCESS;
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}
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/**
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Update the Hybrid storage location NVS Area if Hybrid Storage device is present
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**/
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EFI_STATUS
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UpdateHybridStorageLocation (
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VOID
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)
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{
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VOID *Hob;
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PCH_HYBRIDSTORAGE_HOB *HybridStorageHob;
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Hob = GetFirstGuidHob (&gHybridStorageHobGuid);
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if (Hob == NULL) {
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return EFI_NOT_FOUND;
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}
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HybridStorageHob = (PCH_HYBRIDSTORAGE_HOB *) GET_GUID_HOB_DATA (Hob);
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mPchNvsAreaProtocol.Area->HybridStorageLocation = HybridStorageHob->HybridStorageLocation;
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return EFI_SUCCESS;
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}
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/**
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PCH ACPI initialization before Boot Sript Table is closed
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It update ACPI table and ACPI NVS area.
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@param[in] Event A pointer to the Event that triggered the callback.
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@param[in] Context A pointer to private data registered with the callback function.
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**/
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VOID
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EFIAPI
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PchAcpiOnEndOfDxe (
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IN EFI_EVENT Event,
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IN VOID *Context
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)
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{
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DEBUG ((DEBUG_INFO, "PchAcpiOnEndOfDxe() Start\n"));
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///
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/// Closed the event to avoid call twice when launch shell
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///
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gBS->CloseEvent (Event);
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//
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// Init HDA Audio ACPI tables
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//
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PchHdAudioAcpiInit ();
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//
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// Update ASL definitions for SerialIo devices.
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//
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UpdateSerialIoAcpiData ();
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UpdateCnviAcpiData ();
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#if FixedPcdGet8(PcdEmbeddedEnable) == 0x1
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UpdateTimedGpioSetup();
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#endif
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//
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// Update Pch Nvs Area
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//
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PchUpdateNvsArea ();
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DEBUG ((DEBUG_INFO, "PchAcpiOnEndOfDxe() End\n"));
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return;
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}
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/**
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Initialize Pch acpi
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@param[in] ImageHandle Handle for the image of this driver
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@retval EFI_SUCCESS The function completed successfully
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@retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver
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**/
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EFI_STATUS
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EFIAPI
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PchAcpiInit (
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IN EFI_HANDLE ImageHandle
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)
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{
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EFI_STATUS Status;
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EFI_EVENT EndOfDxeEvent;
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DEBUG ((DEBUG_INFO, "Install PCH NVS protocol\n"));
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Status = (gBS->AllocatePool) (EfiACPIMemoryNVS, sizeof (PCH_NVS_AREA), (VOID **) &mPchNvsAreaProtocol.Area);
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ASSERT_EFI_ERROR (Status);
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ZeroMem ((VOID *) mPchNvsAreaProtocol.Area, sizeof (PCH_NVS_AREA));
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Status = gBS->InstallMultipleProtocolInterfaces (
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&ImageHandle,
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&gPchNvsAreaProtocolGuid,
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&mPchNvsAreaProtocol,
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NULL
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);
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ASSERT_EFI_ERROR (Status);
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///
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/// Update the NVS Area after RST PCIe Storage Remapping
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///
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PchUpdateNvsAreaAfterRemapping ();
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UpdateHybridStorageLocation ();
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//
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// Register an end of DXE event for PCH ACPI to do tasks before invoking any UEFI drivers,
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// applications, or connecting consoles,...
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//
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Status = gBS->CreateEventEx (
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EVT_NOTIFY_SIGNAL,
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TPL_CALLBACK,
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PchAcpiOnEndOfDxe,
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NULL,
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&gEfiEndOfDxeEventGroupGuid,
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&EndOfDxeEvent
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);
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ASSERT_EFI_ERROR (Status);
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return Status;
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}
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/**
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Update NVS area for PCIe root ports.
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**/
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STATIC
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VOID
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PcieRpUpdateNvsArea (
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VOID
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)
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{
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UINT32 Index;
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for (Index = 0; Index < PCH_MAX_PCIE_CLOCKS; Index++) {
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mPchNvsAreaProtocol.Area->ClockToRootPortMap[Index] = mPchConfigHob->PcieRp.PcieClock[Index].Usage;
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}
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}
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/**
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Update ASL object before Boot
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@retval EFI_STATUS
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@retval EFI_NOT_READY The Acpi protocols are not ready.
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**/
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EFI_STATUS
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PchUpdateNvsArea (
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VOID
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)
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{
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EFI_STATUS Status;
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UINTN Index;
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UINT32 HpetBaseAdress;
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GPIO_GROUP GroupToGpeDwX[3];
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UINT32 GroupDw[3];
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UINTN RpDev;
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UINTN RpFun;
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UINT32 Data32;
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PCH_POLICY_PROTOCOL *PchPolicy;
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GPIO_DXE_CONFIG *GpioDxeConfig;
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UINT64 XdciPciBase;
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UINT64 XdciBar;
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UINT16 PciMemConfig;
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UINT16 TcoBase;
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UINT8 ClearXdciBar = FALSE;
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///
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/// Get PCH Policy Protocol
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///
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Status = gBS->LocateProtocol (&gPchPolicyProtocolGuid, NULL, (VOID **)&PchPolicy);
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ASSERT_EFI_ERROR (Status);
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///
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/// Get GPIO DXE Config Block
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///
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Status = GetConfigBlock ((VOID *)PchPolicy, &gGpioDxeConfigGuid, (VOID *)&GpioDxeConfig);
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ASSERT_EFI_ERROR (Status);
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//
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// Update ASL PCIE port address according to root port device and function
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//
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for (Index = 0; Index < GetPchMaxPciePortNum (); Index++) {
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RpDev = PchPcieRpDevNumber (Index);
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RpFun = PchPcieRpFuncNumber (Index);
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Data32 = ((UINT8) RpDev << 16) | (UINT8) RpFun;
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mPchNvsAreaProtocol.Area->RpAddress[Index] = Data32;
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//
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// Update Maximum Snoop Latency and Maximum No-Snoop Latency values for PCIE
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//
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mPchNvsAreaProtocol.Area->PcieLtrMaxSnoopLatency[Index] = mPchConfigHob->PcieRp.RootPort[Index].PcieRpCommonConfig.PcieRpLtrConfig.LtrMaxSnoopLatency;
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mPchNvsAreaProtocol.Area->PcieLtrMaxNoSnoopLatency[Index] = mPchConfigHob->PcieRp.RootPort[Index].PcieRpCommonConfig.PcieRpLtrConfig.LtrMaxNoSnoopLatency;
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}
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//
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// Update PCHS.
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//
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mPchNvsAreaProtocol.Area->PchSeries = PchSeries ();
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//
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// Update PCHG.
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//
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mPchNvsAreaProtocol.Area->PchGeneration = (UINT16) PchGeneration ();
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//
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// Update PSTP.
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//
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mPchNvsAreaProtocol.Area->PchStepping = (UINT16) PchStepping ();
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//
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// Update HPET base address.
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//
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PchHpetBaseGet (&HpetBaseAdress);
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mPchNvsAreaProtocol.Area->HPTE = TRUE; // @todo remove the NVS, since it's always enabled.
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mPchNvsAreaProtocol.Area->HPTB = HpetBaseAdress;
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//
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// Update SBREG_BAR.
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//
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mPchNvsAreaProtocol.Area->SBRG = PCH_PCR_BASE_ADDRESS;
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//
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// Update base address
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//
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mPchNvsAreaProtocol.Area->PMBS = PmcGetAcpiBase ();
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mPchNvsAreaProtocol.Area->PWRM = PmcGetPwrmBase ();
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PchTcoBaseGet (&TcoBase);
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mPchNvsAreaProtocol.Area->TcoBase = TcoBase;
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//
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// Update PCH PID info
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//
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mPchNvsAreaProtocol.Area->IclkPid = PchPcrGetPid (PchIpIclk);
|
|
//
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// Update GPIO device ACPI variables
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//
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mPchNvsAreaProtocol.Area->SGIR = mPchConfigHob->Interrupt.GpioIrqRoute;
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mPchNvsAreaProtocol.Area->GPHD = (UINT8)GpioDxeConfig->HideGpioAcpiDevice;
|
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//
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// Update GPP_X to GPE_DWX mapping.
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//
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GpioGetGroupDwToGpeDwX (
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&GroupToGpeDwX[0], &GroupDw[0],
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&GroupToGpeDwX[1], &GroupDw[1],
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&GroupToGpeDwX[2], &GroupDw[2]
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);
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//
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// GEI0/1/2 and GED0/1/2 are objects for informing how GPIO groups are mapped to GPE0.
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// If Group is mapped to 1-Tier GPE information is also stored on what Group DW
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// is mapped to GPE_DWx. Because GPE_DWx register is 32 bits large if groups have more than
|
// 32 pads only part of it can be mapped.
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//
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// GEIx - GroupIndex mapped to GPE0_DWx
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// GEDx - DoubleWorld part of Group: 0 - pins 31-0, 1 - pins 63-32, ...
|
//
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mPchNvsAreaProtocol.Area->GEI0 = (UINT8) GpioGetGroupIndexFromGroup (GroupToGpeDwX[0]);
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mPchNvsAreaProtocol.Area->GEI1 = (UINT8) GpioGetGroupIndexFromGroup (GroupToGpeDwX[1]);
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mPchNvsAreaProtocol.Area->GEI2 = (UINT8) GpioGetGroupIndexFromGroup (GroupToGpeDwX[2]);
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mPchNvsAreaProtocol.Area->GED0 = (UINT8) GroupDw[0];
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mPchNvsAreaProtocol.Area->GED1 = (UINT8) GroupDw[1];
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mPchNvsAreaProtocol.Area->GED2 = (UINT8) GroupDw[2];
|
|
//
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// SCS Configuration
|
//
|
|
PcieRpUpdateNvsArea ();
|
|
//
|
// SATA configuration.
|
//
|
mPchNvsAreaProtocol.Area->SataPortPresence = GetSataPortPresentStatus (0);
|
DEBUG ((DEBUG_INFO, "SataPortPresence: 0x%x\n", mPchNvsAreaProtocol.Area->SataPortPresence));
|
|
//
|
// CPU SKU
|
//
|
mPchNvsAreaProtocol.Area->CpuSku = 0;
|
mPchNvsAreaProtocol.Area->PsOnEnable = (UINT8)mPchConfigHob->Pm.PsOnEnable;
|
|
for (Index = 0; Index < GetPchMaxPciePortNum (); Index++) {
|
mPchNvsAreaProtocol.Area->LtrEnable[Index] = (UINT8)mPchConfigHob->PcieRp.RootPort[Index].PcieRpCommonConfig.LtrEnable;
|
}
|
|
mPchNvsAreaProtocol.Area->GBES = IsGbePresent ();
|
|
//
|
// Update PCH Trace Hub Mode
|
//
|
mPchNvsAreaProtocol.Area->PchTraceHubMode = (UINT8) mPchConfigHob->PchTraceHub.PchTraceHubMode;
|
|
//
|
// Saving GCTL value into PCH NVS area
|
//
|
|
XdciPciBase = PchXdciPciCfgBase ();
|
|
//
|
// Determine Base address for Base address register (Offset 0x10)
|
//
|
if (PciSegmentRead32 (XdciPciBase) != 0xFFFFFFFF) {
|
|
XdciBar = PciSegmentRead32 (XdciPciBase + PCI_BASE_ADDRESSREG_OFFSET) & 0xFFFFFFF0;
|
|
if ((PciSegmentRead32 (XdciPciBase + PCI_BASE_ADDRESSREG_OFFSET) & B_PCI_BAR_MEMORY_TYPE_MASK) == B_PCI_BAR_MEMORY_TYPE_64) {
|
XdciBar += (UINT64)PciSegmentRead32 (XdciPciBase + (PCI_BASE_ADDRESSREG_OFFSET + 4)) << 32;
|
}
|
|
if (XdciBar == 0x0) {
|
ClearXdciBar = TRUE;
|
PciSegmentWrite32 ((XdciPciBase + PCI_BASE_ADDRESSREG_OFFSET), PcdGet32 (PcdSiliconInitTempMemBaseAddr));
|
XdciBar = PciSegmentRead32 (XdciPciBase + PCI_BASE_ADDRESSREG_OFFSET) & 0xFFFFFFF0;
|
|
if ((PciSegmentRead32 (XdciPciBase + PCI_BASE_ADDRESSREG_OFFSET) & B_PCI_BAR_MEMORY_TYPE_MASK) == B_PCI_BAR_MEMORY_TYPE_64) {
|
XdciBar += (UINT64)PciSegmentRead32 (XdciPciBase + (PCI_BASE_ADDRESSREG_OFFSET + 4)) << 32;
|
}
|
}
|
|
//
|
// Enable Pci Memconfig to read the correct value for GCTL register
|
//
|
PciMemConfig = PciSegmentRead16 (XdciPciBase + PCI_COMMAND_OFFSET);
|
PciSegmentWrite16 (XdciPciBase + PCI_COMMAND_OFFSET, PciMemConfig | (EFI_PCI_COMMAND_BUS_MASTER | EFI_PCI_COMMAND_MEMORY_SPACE));
|
|
mPchNvsAreaProtocol.Area->PchxDCIPwrDnScale = MmioRead32(XdciBar + R_XDCI_MEM_GCTL);
|
DEBUG ((DEBUG_INFO, "PchxDCIPwrDnScale 0x%x\n", (UINT64)mPchNvsAreaProtocol.Area->PchxDCIPwrDnScale));
|
//
|
// Disable Pci Memconfig & clear Base address
|
//
|
PciSegmentWrite16(XdciPciBase + PCI_COMMAND_OFFSET, PciMemConfig);
|
|
if (ClearXdciBar == TRUE) {
|
PciSegmentWrite32 ((XdciPciBase + PCI_BASE_ADDRESSREG_OFFSET), 0x0);
|
PciSegmentWrite32 ((XdciPciBase + (PCI_BASE_ADDRESSREG_OFFSET + 4)), 0x0);
|
}
|
}
|
|
return Status;
|
}
|
