/** @file
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Pch information library for TGL.
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All function in this library is available for PEI, DXE, and SMM,
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But do not support UEFI RUNTIME environment call.
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Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Uefi/UefiBaseType.h>
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#include <Library/PchInfoLib.h>
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#include "PchInfoLibPrivate.h"
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#include <Library/PrintLib.h>
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#include <Register/PchRegsLpc.h>
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/**
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Print Pch Stepping String
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@param[out] Buffer Output buffer of string
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@param[in] BufferSize Buffer Size
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@param[in] PchStep Pch Stepping Type
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@retval VOID
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**/
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VOID
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PchPrintSteppingStr (
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OUT CHAR8 *Buffer,
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IN UINT32 BufferSize,
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IN PCH_STEPPING PchStep
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)
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{
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AsciiSPrint (Buffer, BufferSize, "%c%c", 'A' + (PchStep >> 4), '0' + (PchStep & 0xF));
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}
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/**
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Return Pch Generation
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@retval PCH_GENERATION Pch Generation
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**/
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PCH_GENERATION
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PchGeneration (
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VOID
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)
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{
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return TGL_PCH;
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}
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/**
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Get PCH series ASCII string.
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@retval PCH Series string
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**/
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CHAR8*
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PchGetSeriesStr (
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VOID
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)
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{
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switch (PchSeries ()) {
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case PCH_LP:
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return "TGL PCH-LP";
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default:
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return NULL;
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}
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}
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/**
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Get Pch Maximum Pcie Clock Number
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@retval Pch Maximum Pcie Clock Number
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**/
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UINT8
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GetPchMaxPcieClockNum (
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VOID
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)
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{
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return 7;
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}
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/**
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Get Pch Maximum Pcie ClockReq Number
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@retval Pch Maximum Pcie ClockReq Number
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**/
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UINT8
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GetPchMaxPcieClockReqNum (
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VOID
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)
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{
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return GetPchMaxPcieClockNum ();
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}
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/**
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Get Pch Maximum Type C Port Number
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@retval Pch Maximum Type C Port Number
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**/
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UINT8
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GetPchMaxTypeCPortNum (
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VOID
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)
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{
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switch (PchSeries ()) {
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case PCH_LP:
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return 4;
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default:
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return 0;
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}
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}
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/**
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Check whether integrated LAN controller is supported by PCH Series.
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@retval TRUE GbE is supported in current PCH
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@retval FALSE GbE is not supported on current PCH
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**/
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BOOLEAN
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PchIsGbeSupported (
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VOID
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)
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{
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return TRUE;
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}
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/**
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Check whether integrated TSN is supported by PCH Series.
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@retval TRUE TSN is supported in current PCH
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@retval FALSE TSN is not supported on current PCH
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**/
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BOOLEAN
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PchIsTsnSupported (
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VOID
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)
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{
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#if FixedPcdGet8(PcdEmbeddedEnable) == 0x1
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return TRUE;
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#else
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return FALSE;
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#endif
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}
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/**
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Check whether ISH is supported by PCH Series.
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@retval TRUE ISH is supported in current PCH
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@retval FALSE ISH is not supported on current PCH
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**/
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BOOLEAN
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PchIsIshSupported (
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VOID
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)
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{
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return TRUE;
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}
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/**
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Get Pch Maximum Pcie Root Port Number
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@retval Pch Maximum Pcie Root Port Number
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**/
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UINT8
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GetPchMaxPciePortNum (
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VOID
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)
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{
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switch (PchSeries ()) {
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case PCH_LP:
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return 12;
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default:
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return 0;
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}
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}
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/**
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Get Pch Maximum Hda Dmic Link
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@retval Pch Maximum Hda Dmic Link
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**/
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UINT8
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GetPchHdaMaxDmicLinkNum (
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VOID
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)
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{
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return 2;
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}
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/**
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Get Pch Maximum Hda Sndw Link
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@retval Pch Maximum Hda Sndw Link
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**/
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UINT8
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GetPchHdaMaxSndwLinkNum (
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VOID
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)
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{
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return 4;
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}
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/**
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Get Pch Maximum Hda Ssp Link
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@retval Pch Maximum Hda Ssp Link
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**/
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UINT8
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GetPchHdaMaxSspLinkNum (
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VOID
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)
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{
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return 3;
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}
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/**
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Check if given Audio Interface is supported
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@param[in] AudioLinkType Link type support to be checked
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@param[in] AudioLinkIndex Link number
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@retval TRUE Link supported
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@retval FALSE Link not supported
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**/
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BOOLEAN
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IsAudioInterfaceSupported (
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IN HDAUDIO_LINK_TYPE AudioLinkType,
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IN UINT32 AudioLinkIndex
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)
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{
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//
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// Interfaces supported:
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// 1. HDA Link (SDI0/SDI1)
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// 2. Display Audio Link (SDI2)
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// 3. SSP[0-5]
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// 4. SNDW[1-4]
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//
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switch (AudioLinkType) {
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case HdaLink:
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case HdaIDispLink:
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return TRUE;
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case HdaDmic:
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if (AudioLinkIndex < 2) {
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return TRUE;
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} else {
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return FALSE;
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}
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case HdaSsp:
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if (AudioLinkIndex < 6) {
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return TRUE;
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} else {
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return FALSE;
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}
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case HdaSndw:
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if (AudioLinkIndex < 1) {
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return TRUE;
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} else if (AudioLinkIndex < 4) {
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return TRUE;
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} else {
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return FALSE;
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}
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default:
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return FALSE;
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}
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}
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/**
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Check if given Display Audio Link T-Mode is supported
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@param[in] Tmode T-mode support to be checked
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@retval TRUE T-mode supported
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@retval FALSE T-mode not supported
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**/
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BOOLEAN
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IsAudioIDispTmodeSupported (
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IN HDAUDIO_IDISP_TMODE Tmode
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)
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{
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//
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// iDisplay Audio Link T-mode support per PCH Generation/Series:
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// 1. 2T - TGL-LP/H/N
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// 2. 4T - TGL-LP (default), TGL-H, TGL-N
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// 3. 8T - TGL-H, TGL-N (default)
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// 4. 16T - TGL-H, TGL-N (not-POR)
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//
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switch (Tmode) {
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case HdaIDispMode1T:
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return FALSE;
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case HdaIDispMode2T:
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case HdaIDispMode4T:
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case HdaIDispMode8T:
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return TRUE;
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case HdaIDispMode16T:
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return FALSE;
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default:
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return FALSE;
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}
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}
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/**
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Get Pch Usb2 Maximum Physical Port Number
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@retval Pch Usb2 Maximum Physical Port Number
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**/
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UINT8
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GetPchUsb2MaxPhysicalPortNum(
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VOID
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)
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{
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switch (PchSeries()) {
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case PCH_LP:
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return 10;
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default:
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return 0;
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}
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}
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/**
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Get Pch Maximum Usb2 Port Number of XHCI Controller
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@retval Pch Maximum Usb2 Port Number of XHCI Controller
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**/
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UINT8
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GetPchXhciMaxUsb2PortNum(
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VOID
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)
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{
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switch (PchSeries()) {
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case PCH_LP:
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return 12;
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default:
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return 0;
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}
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}
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/**
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Get Pch Maximum Usb3 Port Number of XHCI Controller
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@retval Pch Maximum Usb3 Port Number of XHCI Controller
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**/
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UINT8
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GetPchXhciMaxUsb3PortNum(
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VOID
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)
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{
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switch (PchSeries()) {
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case PCH_LP:
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return 4;
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default:
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return 0;
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}
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}
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/**
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Gets the maximum number of UFS controller supported by this chipset.
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@return Number of supported UFS controllers
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**/
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UINT8
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PchGetMaxUfsNum (
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VOID
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)
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{
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return 2;
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}
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/**
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Check if this chipset supports eMMC controller
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@retval BOOLEAN TRUE if supported, FALSE otherwise
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**/
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BOOLEAN
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IsPchEmmcSupported (
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VOID
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)
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{
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return FALSE;
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}
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/**
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Check if this chipset supports SD controller
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@retval BOOLEAN TRUE if supported, FALSE otherwise
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**/
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BOOLEAN
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IsPchSdCardSupported (
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VOID
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)
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{
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return FALSE;
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}
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/**
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Check if this chipset supports THC controller
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@retval BOOLEAN TRUE if supported, FALSE otherwise
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**/
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BOOLEAN
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IsPchThcSupported (
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VOID
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)
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{
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return TRUE;
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}
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/**
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Check if this chipset supports HSIO BIOS Sync
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@retval BOOLEAN TRUE if supported, FALSE otherwise
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**/
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BOOLEAN
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IsPchChipsetInitSyncSupported (
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VOID
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)
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{
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return TRUE;
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}
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/**
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Check if link between PCH and CPU is an P-DMI
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@retval TRUE P-DMI link
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@retval FALSE Not an P-DMI link
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**/
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BOOLEAN
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IsPchWithPdmi (
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VOID
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)
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{
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return FALSE;
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}
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/**
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Check whether ATX Shutdown (PS_ON) is supported.
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@retval TRUE ATX Shutdown (PS_ON) is supported in PCH
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@retval FALSE ATX Shutdown (PS_ON) is not supported by PCH
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**/
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BOOLEAN
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IsPchPSOnSupported (
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VOID
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)
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{
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return FALSE;
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}
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/**
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Check if link between PCH and CPU is an OP-DMI
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@retval TRUE OP-DMI link
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@retval FALSE Not an OP-DMI link
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**/
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BOOLEAN
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IsPchWithOpdmi (
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VOID
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)
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{
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return TRUE;
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}
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/**
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Check if link between PCH and CPU is an F-DMI
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@retval TRUE F-DMI link
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@retval FALSE Not an F-DMI link
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**/
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BOOLEAN
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IsPchWithFdmi (
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VOID
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)
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{
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return FALSE;
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}
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/**
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Get Pch Maximum ISH UART Controller number
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@retval Pch Maximum ISH UART controllers number
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**/
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UINT8
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GetPchMaxIshUartControllersNum (
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VOID
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)
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{
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return 2;
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}
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/**
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Get Pch Maximum ISH I2C Controller number
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@retval Pch Maximum ISH I2C controllers number
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**/
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UINT8
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GetPchMaxIshI2cControllersNum (
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VOID
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)
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{
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return 3;
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}
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/**
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Get Pch Maximum ISH I3C Controller number
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@retval Pch Maximum ISH I3C controllers number
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**/
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UINT8
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GetPchMaxIshI3cControllersNum (
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VOID
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)
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{
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return 0;
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}
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/**
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Get Pch Maximum ISH SPI Controller number
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@retval Pch Maximum ISH SPI controllers number
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**/
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UINT8
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GetPchMaxIshSpiControllersNum (
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VOID
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)
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{
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return 1;
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}
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/**
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Get Pch Maximum ISH SPI Controller Cs pins number
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@retval Pch Maximum ISH SPI controller Cs pins number
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**/
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UINT8
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GetPchMaxIshSpiControllerCsPinsNum (
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VOID
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)
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{
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return 1;
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}
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/**
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Get Pch Maximum ISH GP number
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@retval Pch Maximum ISH GP number
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**/
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UINT8
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GetPchMaxIshGpNum (
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VOID
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)
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{
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return 8;
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}
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/**
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Get Pch Maximum Serial IO I2C controllers number
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@retval Pch Maximum Serial IO I2C controllers number
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**/
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UINT8
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GetPchMaxSerialIoI2cControllersNum (
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VOID
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)
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{
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return 6;
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}
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/**
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Get Pch Maximum Serial IO SPI controllers number
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@retval Pch Maximum Serial IO SPI controllers number
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**/
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UINT8
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GetPchMaxSerialIoSpiControllersNum (
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VOID
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)
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{
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return 4;
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}
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/**
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Get Pch Maximum Serial IO UART controllers number
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@retval Pch Maximum Serial IO UART controllers number
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**/
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UINT8
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GetPchMaxSerialIoUartControllersNum (
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VOID
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)
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{
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return 4;
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}
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/**
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Get Pch Maximum Serial IO SPI Chip Selects count
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@retval Pch Maximum Serial IO SPI Chip Selects number
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**/
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UINT8
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GetPchMaxSerialIoSpiChipSelectsNum (
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VOID
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)
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{
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return 2;
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}
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/**
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Get Pch Maximum ME Applet count
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@retval Pch Maximum ME Applet number
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**/
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UINT8
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GetPchMaxMeAppletCount (
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VOID
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)
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{
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return 31;
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}
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/**
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Get Pch Maximum ME Session count
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@retval Pch Maximum ME Sesion number
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**/
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UINT8
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GetPchMaxMeSessionCount (
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VOID
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)
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{
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return 16;
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}
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/**
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Get Pch Maximum THC count
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@retval Pch Maximum THC count number
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**/
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UINT8
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GetPchMaxThcCount (
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VOID
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)
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{
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return 2;
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}
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/**
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Returns a frequency of the sosc_clk signal.
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All SATA controllers on the system are assumed to
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work on the same sosc_clk frequency.
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@retval Frequency of the sosc_clk signal.
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**/
|
SATA_SOSC_CLK_FREQ
|
GetSataSoscClkFreq (
|
VOID
|
)
|
{
|
return SataSosc100Mhz;
|
}
|
|
/**
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Check if SATA support should be awake after function disable
|
|
@retval TRUE
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@retval FALSE
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**/
|
BOOLEAN
|
IsSataSupportWakeAfterFunctionDisable (
|
VOID
|
)
|
{
|
return TRUE;
|
}
|
|
/**
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Returns USB2 PHY Reference Clock frequency value used by PCH
|
This defines what electrical tuning parameters shall be used
|
during USB2 PHY initialization programming
|
|
@retval Frequency reference clock for USB2 PHY
|
**/
|
USB2_PHY_REF_FREQ
|
GetUsb2PhyRefFreq (
|
VOID
|
)
|
{
|
return FREQ_19_2;
|
}
|
|
/**
|
Check if SPI in a given PCH generation supports an Extended BIOS Range Decode
|
|
@retval TRUE or FALSE if PCH supports Extended BIOS Range Decode
|
**/
|
BOOLEAN
|
IsExtendedBiosRangeDecodeSupported (
|
VOID
|
)
|
{
|
return TRUE;
|
}
|
|
#define SPI_PCH_LP_DMI_TARGET 0x23A8
|
|
/**
|
Returns DMI target for current PCH SPI
|
|
@retval PCH SPI DMI target value
|
**/
|
UINT16
|
GetPchSpiDmiTarget (
|
VOID
|
)
|
{
|
return SPI_PCH_LP_DMI_TARGET;
|
}
|
