/** @file
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Register names for PCH LPC/eSPI device
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Conventions:
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- Register definition format:
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Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
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- Prefix:
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Definitions beginning with "R_" are registers
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Definitions beginning with "B_" are bits within registers
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Definitions beginning with "V_" are meaningful values within the bits
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Definitions beginning with "S_" are register size
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Definitions beginning with "N_" are the bit position
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- [GenerationName]:
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Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
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Register name without GenerationName applies to all generations.
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- [ComponentName]:
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This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
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Register name without ComponentName applies to all components.
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Register that is specific to -LP denoted by "_PCH_LP_" in component name.
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- SubsystemName:
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This field indicates the subsystem name of the component that the register belongs to
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(e.g. PCIE, USB, SATA, GPIO, PMC etc.).
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- RegisterSpace:
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MEM - MMIO space register of subsystem.
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IO - IO space register of subsystem.
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PCR - Private configuration register of subsystem.
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CFG - PCI configuration space register of subsystem.
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- RegisterName:
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Full register name.
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Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _PCH_REGS_LPC_H_
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#define _PCH_REGS_LPC_H_
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#define B_LPC_CFG_DID 0xFFE0
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//
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// PCI to LPC Bridge Registers
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//
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#define R_LPC_CFG_IOD 0x80
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#define V_LPC_CFG_IOD_COMB_2F8 1
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#define V_LPC_CFG_IOD_COMA_3F8 0
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#define V_LPC_CFG_IOD_COMA_2F8 1
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#define R_LPC_CFG_IOE 0x82
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#define B_LPC_CFG_IOE_SE BIT12 ///< Super I/O Enable, Enables decoding of I/O locations 2Eh and 2Fh to LPC.
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#define B_LPC_CFG_IOE_KE BIT10 ///< Keyboard Enable, Enables decoding of the keyboard I/O locations 60h and 64h to LPC.
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#define B_LPC_CFG_IOE_PPE BIT2 ///< Parallel Port Enable, Enables decoding of the LPT range to LPC. Range is selected by LIOD.LPT.
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#define B_LPC_CFG_IOE_CBE BIT1 ///< Com Port B Enable, Enables decoding of the COMB range to LPC. Range is selected LIOD.CB.
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#define B_LPC_CFG_IOE_CAE BIT0 ///< Com Port A Enable, Enables decoding of the COMA range to LPC. Range is selected LIOD.CA.
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#define R_LPC_CFG_ULKMC 0x94
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#define B_LPC_CFG_ULKMC_A20PASSEN BIT5
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#define B_LPC_CFG_ULKMC_64WEN BIT3
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#define B_LPC_CFG_ULKMC_64REN BIT2
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#define B_LPC_CFG_ULKMC_60WEN BIT1
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#define B_LPC_CFG_ULKMC_60REN BIT0
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#define R_LPC_CFG_LGMR 0x98
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#define B_LPC_CFG_LGMR_MA 0xFFFF0000
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#define B_LPC_CFG_LGMR_LMRD_EN BIT0
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#define R_ESPI_CFG_CS1IORE 0xA0
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#define R_ESPI_CFG_CS1GMR1 0xA8
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#define R_LPC_CFG_BDE 0xD8 ///< BIOS decode enable
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//
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// APM Registers
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//
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#define R_PCH_IO_APM_CNT 0xB2
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#define R_PCH_IO_APM_STS 0xB3
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#define R_LPC_CFG_BC 0xDC ///< Bios Control
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#define S_LPC_CFG_BC 1
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#define N_LPC_CFG_BC_LE 1
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#define B_LPC_CFG_BC_WPD BIT0 ///< Write Protect Disable
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#define R_ESPI_CFG_PCBC 0xDC ///< Peripheral Channel BIOS Control
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#define S_ESPI_CFG_PCBC 4 ///< Peripheral Channel BIOS Control register size
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#define B_ESPI_CFG_PCBC_BWRE BIT11 ///< BIOS Write Report Enable
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#define B_ESPI_CFG_PCBC_BWRS BIT10 ///< BIOS Write Report Status
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#define B_ESPI_CFG_PCBC_BWPDS BIT8 ///< BIOS Write Protect Disable Status
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#define N_ESPI_CFG_PCBC_BWPDS 8 ///< BIOS Write Protect Disable Status bit position
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#define B_ESPI_CFG_PCBC_ESPI_EN BIT2 ///< eSPI Enable Pin Strap
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#define B_ESPI_CFG_PCBC_LE BIT1 ///< Lock Enable
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#define N_ESPI_CFG_PCBC_LE 1
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//
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// eSPI slave registers
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//
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#define B_ESPI_SLAVE_BME BIT2 ///< Bus Master Enable
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//
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// Reset Generator I/O Port
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//
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#define R_PCH_IO_RST_CNT 0xCF9
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#define V_PCH_IO_RST_CNT_FULLRESET 0x0E
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#define V_PCH_IO_RST_CNT_HARDRESET 0x06
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//
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// eSPI PCR Registers
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//
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#define R_ESPI_PCR_SLV_CFG_REG_CTL 0x4000 ///< Slave Configuration Register and Link Control
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#define B_ESPI_PCR_SLV_CFG_REG_CTL_SCRE BIT31 ///< Slave Configuration Register Access Enable
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#define B_ESPI_PCR_SLV_CFG_REG_CTL_SCRS (BIT30 | BIT29 | BIT28) ///< Slave Configuration Register Access Status
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#define N_ESPI_PCR_SLV_CFG_REG_CTL_SCRS 28 ///< Slave Configuration Register Access Status bit position
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#define B_ESPI_PCR_SLV_CFG_REG_CTL_SBLCL BIT27 ///< IOSF-SB eSPI Link Configuration Lock
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#define V_ESPI_PCR_SLV_CFG_REG_CTL_SCRS_NOERR 7 ///< No errors (transaction completed successfully)
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#define B_ESPI_PCR_SLV_CFG_REG_CTL_SID (BIT20 | BIT19) ///< Slave ID
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#define N_ESPI_PCR_SLV_CFG_REG_CTL_SID 19 ///< Slave ID bit position
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#define B_ESPI_PCR_SLV_CFG_REG_CTL_SCRT (BIT17 | BIT16) ///< Slave Configuration Register Access Type
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#define N_ESPI_PCR_SLV_CFG_REG_CTL_SCRT 16 ///< Slave Configuration Register Access Type bit position
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#define B_ESPI_PCR_SLV_CFG_REG_CTL_SCRA 0x00000FFF ///< Slave Configuration Register Address
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#define R_ESPI_PCR_SLV_CFG_REG_DATA 0x4004 ///< Slave Configuration Register Data
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#define R_ESPI_PCR_PCERR_SLV0 0x4020 ///< Peripheral Channel Error for Slave 0
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#define B_ESPI_PCR_PCERR_PCURD BIT24 ///< Peripheral Channel Unsupported Request Detected
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#define R_ESPI_PCR_VWERR_SLV0 0x4030 ///< Virtual Wire Channel Error for Slave 0
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#define R_ESPI_PCR_FCERR_SLV0 0x4040 ///< Flash Access Channel Error for Slave 0
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#define B_ESPI_PCR_FCERR_SAFBLK BIT17 ///< SAF Blocked (SAFBLK)
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#define B_ESPI_PCR_XERR_XNFEE (BIT14 | BIT13) ///< Non-Fatal Error Reporting Enable bits
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#define N_ESPI_PCR_XERR_XNFEE 13 ///< Non-Fatal Error Reporting Enable bit position
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#define V_ESPI_PCR_XERR_XNFEE_SMI 3 ///< Enable Non-Fatal Error Reporting as SMI
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#define B_ESPI_PCR_XERR_XNFES BIT12 ///< Fatal Error Status
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#define B_ESPI_PCR_XERR_XFEE (BIT6 | BIT5) ///< Fatal Error Reporting Enable bits
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#define N_ESPI_PCR_XERR_XFEE 5 ///< Fatal Error Reporting Enable bit position
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#define V_ESPI_PCR_XERR_XFEE_SMI 3 ///< Enable Fatal Error Reporting as SMI
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#define B_ESPI_PCR_XERR_XFES BIT4 ///< Fatal Error Status
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#define S_ESPI_PCR_XERR 4 ///< Channel register sizes
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#define B_ESPI_PCR_PCERR_SLV0_PCURD BIT24 ///< Peripheral Channel Unsupported Request Detected
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#define R_ESPI_PCR_LNKERR_SLV0 0x4050 ///< Link Error for Slave 0
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#define S_ESPI_PCR_LNKERR_SLV0 4 ///< Link Error for Slave 0 register size
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#define B_ESPI_PCR_LNKERR_SLV0_SLCRR BIT31 ///< eSPI Link and Slave Channel Recovery Required
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#define B_ESPI_PCR_LNKERR_SLV0_LFET1E (BIT22 | BIT21) ///< Fatal Error Type 1 Reporting Enable
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#define N_ESPI_PCR_LNKERR_SLV0_LFET1E 21 ///< Fatal Error Type 1 Reporting Enable bit position
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#define V_ESPI_PCR_LNKERR_SLV0_LFET1E_SMI 3 ///< Enable Fatal Error Type 1 Reporting as SMI
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#define B_ESPI_PCR_LNKERR_SLV0_LFET1S BIT20 ///< Link Fatal Error Type 1 Status
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#define R_ESPI_PCR_LNKERR_SLV1 0x4054 ///< Link Error for Slave 1
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#define R_ESPI_PCR_CFG_VAL 0xC00C ///< ESPI Enabled Strap
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#define B_ESPI_PCR_CFG_VAL_ESPI_EN BIT0 ///< ESPI Enabled Strap bit position
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#define R_ESPI_PCR_SOFTSTRAPS 0xC210 ///< eSPI Sofstraps Register 0
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#define B_ESPI_PCR_SOFTSTRAPS_CS1_EN BIT12 ///< CS1# Enable
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#endif
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