/** @file
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APIs of PCH PCIE SMI Dispatch Protocol.
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Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _PCH_PCIE_SMI_DISPATCH_PROTOCOL_H_
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#define _PCH_PCIE_SMI_DISPATCH_PROTOCOL_H_
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//
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// Extern the GUID for protocol users.
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//
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extern EFI_GUID gPchPcieSmiDispatchProtocolGuid;
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//
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// Forward reference for ANSI C compatibility
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//
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typedef struct _PCH_PCIE_SMI_DISPATCH_PROTOCOL PCH_PCIE_SMI_DISPATCH_PROTOCOL;
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typedef enum {
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PchRpIndex0 = 0,
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PchRpIndex1 = 1,
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PchRpIndex2 = 2,
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PchRpIndex3 = 3,
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PchRpIndex4 = 4,
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PchRpIndex5 = 5,
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PchRpIndex6 = 6,
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PchRpIndex7 = 7,
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PchRpIndex8 = 8,
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PchRpIndex9 = 9,
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PchRpIndex10 = 10,
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PchRpIndex11 = 11,
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PchRpIndex12 = 12,
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PchRpIndex13 = 13,
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PchRpIndex14 = 14,
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PchRpIndex15 = 15,
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PchRpIndex16 = 16,
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PchRpIndex17 = 17,
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PchRpIndex18 = 18,
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PchRpIndex19 = 19,
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PchRpIndex20 = 20,
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PchRpIndex21 = 21,
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PchRpIndex22 = 22,
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PchRpIndex23 = 23,
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/**
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Quantity of PCH and CPU PCIe ports, as well as their encoding in this enum, may change between
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silicon generations and series. Do not assume that PCH port 0 will be always encoded by 0.
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Instead, it is recommended to use (PchRpIndex0 + PchPortIndex) style to be forward-compatible
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**/
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CpuRpIndex0 = 0x40,
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CpuRpIndex1 = 0x41,
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CpuRpIndex2 = 0x42,
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CpuRpIndex3 = 0x43
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} PCIE_COMBINED_RPINDEX;
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//
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// Member functions
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//
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typedef struct {
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UINT8 RpIndex; ///< Root port index (0-based), 0: RP1, 1: RP2, n: RP(N+1)
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UINT8 BusNum; ///< Root port pci bus number
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UINT8 DevNum; ///< Root port pci device number
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UINT8 FuncNum; ///< Root port pci function number
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} PCH_PCIE_SMI_RP_CONTEXT;
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/**
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Callback function for an PCH PCIE RP SMI handler dispatch.
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@param[in] DispatchHandle The unique handle assigned to this handler by register function.
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@param[in] RpContext Pointer of PCH PCIE Root Port context.
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**/
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typedef
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VOID
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(EFIAPI *PCH_PCIE_SMI_RP_DISPATCH_CALLBACK) (
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IN EFI_HANDLE DispatchHandle,
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IN PCH_PCIE_SMI_RP_CONTEXT *RpContext
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);
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/**
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Register a child SMI source dispatch function for PCH PCIERP SMI events.
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@param[in] This Protocol instance pointer.
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@param[in] DispatchFunction Pointer to dispatch function to be invoked for
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this SMI source
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@param[in] RpIndex Refer PCIE_COMBINED_RPINDEX for PCH RP index and CPU RP index.
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0: RP1, 1: RP2, n: RP(N+1)
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@param[out] DispatchHandle Handle of dispatch function, for when interfacing
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with the parent SMM driver.
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@retval EFI_SUCCESS The dispatch function has been successfully
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registered and the SMI source has been enabled.
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@retval EFI_DEVICE_ERROR The driver was unable to enable the SMI source.
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@retval EFI_OUT_OF_RESOURCES Not enough memory (system or SMM) to manage this child.
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@retval EFI_ACCESS_DENIED Return access denied if the EndOfDxe event has been triggered
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**/
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typedef
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EFI_STATUS
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(EFIAPI *PCH_PCIE_SMI_RP_DISPATCH_REGISTER) (
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IN PCH_PCIE_SMI_DISPATCH_PROTOCOL *This,
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IN PCH_PCIE_SMI_RP_DISPATCH_CALLBACK DispatchFunction,
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IN UINTN RpIndex,
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OUT EFI_HANDLE *DispatchHandle
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);
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/**
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Unregister a child SMI source dispatch function with a parent PCIE SMM driver
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@param[in] This Protocol instance pointer.
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@param[in] DispatchHandle Handle of dispatch function to deregister.
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@retval EFI_SUCCESS The dispatch function has been successfully
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unregistered and the SMI source has been disabled
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if there are no other registered child dispatch
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functions for this SMI source.
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@retval EFI_INVALID_PARAMETER Handle is invalid.
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@retval EFI_ACCESS_DENIED Return access denied if the EndOfDxe event has been triggered
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**/
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typedef
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EFI_STATUS
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(EFIAPI *PCH_PCIE_SMI_DISPATCH_UNREGISTER) (
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IN PCH_PCIE_SMI_DISPATCH_PROTOCOL *This,
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IN EFI_HANDLE DispatchHandle
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);
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/**
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Interface structure for PCH PCIE SMIs Dispatch Protocol
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The PCH PCIE SMI DISPATCH PROTOCOL provides the ability to dispatch function for PCH PCIE related SMIs.
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It contains SMI types of HotPlug, LinkActive, and Link EQ.
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**/
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struct _PCH_PCIE_SMI_DISPATCH_PROTOCOL {
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/**
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This member specifies the revision of this structure. This field is used to
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indicate backwards compatible changes to the protocol.
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**/
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UINT8 Revision;
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/**
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Smi unregister function for PCH PCIE SMI DISPATCH PROTOCOL.
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**/
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PCH_PCIE_SMI_DISPATCH_UNREGISTER UnRegister;
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/**
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PcieRpXHotPlug
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The event is triggered when PCIE root port Hot-Plug Presence Detect.
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**/
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PCH_PCIE_SMI_RP_DISPATCH_REGISTER HotPlugRegister;
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/**
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PcieRpXLinkActive
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The event is triggered when Hot-Plug Link Active State Changed.
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**/
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PCH_PCIE_SMI_RP_DISPATCH_REGISTER LinkActiveRegister;
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/**
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PcieRpXLinkEq
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The event is triggered when Device Requests Software Link Equalization.
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**/
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PCH_PCIE_SMI_RP_DISPATCH_REGISTER LinkEqRegister;
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};
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/**
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PCH PCIE SMI dispatch revision number
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Revision 1: Initial version
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**/
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#define PCH_PCIE_SMI_DISPATCH_REVISION 1
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#endif
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