/** @file
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Build time limits of PCH resources.
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Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _PCH_LIMITS_H_
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#define _PCH_LIMITS_H_
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/*
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* Defines povided in this file are indended to be used only where static value
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* is needed. They are set to values which allow to accomodate multiple projects
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* needs. Where runtime usage is possible please used dedicated functions from
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* PchInfoLib to retrieve accurate values
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*/
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//
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// PCIe limits
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//
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#define PCH_MAX_PCIE_ROOT_PORTS 24
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#define PCH_MAX_PCIE_CONTROLLERS 6
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//
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// PCIe clocks limits
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//
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#define PCH_MAX_PCIE_CLOCKS 16
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//
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// RST PCIe Storage Cycle Router limits
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//
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#define PCH_MAX_RST_PCIE_STORAGE_CR 3
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//
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// SATA limits
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//
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#define PCH_MAX_SATA_CONTROLLERS 3
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#define PCH_MAX_SATA_PORTS 8
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//
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// SerialIo limits
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//
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#define PCH_MAX_SERIALIO_I2C_CONTROLLERS 8
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#define PCH_MAX_SERIALIO_SPI_CONTROLLERS 7
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#define PCH_MAX_SERIALIO_SPI_CHIP_SELECTS 2
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#define PCH_MAX_SERIALIO_UART_CONTROLLERS 7
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//
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// ISH limits
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//
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#define PCH_MAX_ISH_GP_PINS 8
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#define PCH_MAX_ISH_UART_CONTROLLERS 2
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#define PCH_MAX_ISH_I2C_CONTROLLERS 3
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#define PCH_MAX_ISH_SPI_CONTROLLERS 1
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#define PCH_MAX_ISH_SPI_CS_PINS 1
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//
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// HDA limits
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//
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#define PCH_MAX_HDA_SDI 2
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#define PCH_MAX_HDA_SSP_LINK_NUM 6
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#define PCH_MAX_HDA_SNDW_LINK_NUM 4
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//
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// Number of eSPI slaves
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//
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#define PCH_MAX_ESPI_SLAVES 2
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#endif // _PCH_LIMITS_H_
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