/** @file
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Serial IO Private Lib implementation - UART part
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All function in this library is available for PEI, DXE, and SMM,
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But do not support UEFI RUNTIME environment call.
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Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Base.h>
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#include <Uefi/UefiBaseType.h>
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#include <Library/IoLib.h>
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#include <Library/BaseLib.h>
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#include <Library/PchInfoLib.h>
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#include <Library/PciSegmentLib.h>
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#include <Library/SerialIoAccessLib.h>
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#include <Library/SerialIoPrivateLib.h>
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#include <IndustryStandard/Pci30.h>
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#include <Register/PchRegs.h>
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#include <Register/SerialIoRegs.h>
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#include <SerialIoPrivateLibInternal.h>
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#include <PchLimits.h>
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#include <Library/PchPciBdfLib.h>
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/**
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Checks if UART is Hidden, and it's Pci Config space available
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@param[in] UartNumber Selects Serial IO UART device
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@retval TRUE UART is in hidden mode
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@retval FALSE UART is not in hidden mode
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**/
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BOOLEAN
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IsSerialIoUartHidden (
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IN UINT8 UartNumber
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)
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{
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if (MmioRead16 (GetSerialIoUartFixedPciCfgAddress (UartNumber) + PCI_DEVICE_ID_OFFSET) == GetSerialIoUartDeviceId (UartNumber)) {
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return TRUE;
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}
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return FALSE;
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}
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/**
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Configures Serial IO Controller before control is passd to the OS
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@param[in] UartNumber UART Number
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@param[in] UartDeviceConfig SerialIo UART Config
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**/
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VOID
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SerialIoUartBootHandler (
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IN UINT8 UartNumber,
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IN SERIAL_IO_UART_CONFIG *UartDeviceConfig
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)
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{
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UINT64 PciCfgBase;
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BOOLEAN TurnOff;
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TurnOff = FALSE;
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//
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// Even if Uart is Hidden and in D3 SerialIoUartLib is capable of setting D0 during each write/read.
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// In case it is required for Os Debug DBG2 must be set to TRUE.
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//
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if (UartDeviceConfig->Mode == SerialIoUartPci || UartDeviceConfig->Mode == SerialIoUartHidden) {
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TurnOff = TRUE;
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}
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//
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// Uart in Com mode will be placed in D3 depending on PG configuration through ACPI _PS3
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//
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if ((UartDeviceConfig->Mode == SerialIoUartDisabled) && (SerialIoUartFuncNumber (UartNumber) == 0x0)) {
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if (SerialIoHigherFunctionsEnabled (SerialIoUartDevNumber (UartNumber))) {
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TurnOff = TRUE;
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}
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}
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if (UartDeviceConfig->DBG2 == TRUE) {
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TurnOff = FALSE;
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}
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if (TurnOff) {
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PciCfgBase = GetSerialIoUartPciCfg (UartNumber);
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SerialIoSetD3 (PciCfgBase);
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if ((UartDeviceConfig->Mode == SerialIoUartPci) || (UartDeviceConfig->Mode == SerialIoUartDisabled)) {
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SerialIoMmioDisable (PciCfgBase, TRUE);
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}
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}
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}
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/**
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Sets Pme Control Status and Command register values required for S3 Boot Script
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@param[in] UartNumber UART Number
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@param[in] UartDeviceConfig SerialIo UART Config
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@param[in/out] S3PciCfgBase S3 Boot Script Pci Config Base
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@param[in/out] Command Pci Command register data to save
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@param[in/out] Pme Pci Pme Control register data to save
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**/
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VOID
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SerialIoUartS3Handler (
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IN UINT8 UartNumber,
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IN SERIAL_IO_UART_CONFIG *UartDeviceConfig,
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IN OUT UINT64 *S3PciCfgBase,
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IN OUT UINT32 *Command,
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IN OUT UINT32 *Pme
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)
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{
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BOOLEAN TurnOff;
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UINT64 PciCfgBase;
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*S3PciCfgBase = 0;
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TurnOff = FALSE;
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if (UartDeviceConfig->Mode == SerialIoUartPci) {
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TurnOff = TRUE;
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}
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if ((UartDeviceConfig->Mode == SerialIoUartDisabled) && (SerialIoUartFuncNumber (UartNumber) == 0x0)) {
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if (SerialIoHigherFunctionsEnabled (SerialIoUartDevNumber (UartNumber))) {
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TurnOff = TRUE;
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}
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}
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if (TurnOff) {
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*S3PciCfgBase = GetSerialIoUartS3PciBase (UartNumber);
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PciCfgBase = GetSerialIoUartPciCfg (UartNumber);
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*Pme = PciSegmentRead32 ((UINTN) PciCfgBase + R_SERIAL_IO_CFG_PME_CTRL_STS);
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*Pme = *Pme | BIT0 | BIT1;
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*Command = PciSegmentRead32 ((UINTN) PciCfgBase + PCI_COMMAND_OFFSET);
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*Command = *Command & (UINT32)~(EFI_PCI_COMMAND_MEMORY_SPACE | EFI_PCI_COMMAND_BUS_MASTER);
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}
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}
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