/** @file
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Serial IO Private Lib implementation.
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All function in this library is available for PEI, DXE, and SMM,
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But do not support UEFI RUNTIME environment call.
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Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Base.h>
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#include <Uefi/UefiBaseType.h>
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#include <Library/IoLib.h>
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#include <Library/BaseLib.h>
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#include <Library/SerialIoAccessLib.h>
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#include <Library/SerialIoPrivateLib.h>
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#include <Library/PciSegmentLib.h>
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#include <Register/PchRegs.h>
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#include <Register/SerialIoRegs.h>
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#include <Include/PcieRegs.h>
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#include <IndustryStandard/Pci30.h>
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#include <PchReservedResources.h>
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/**
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Checks if higher functions are enabled.
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Used for Function 0 Serial Io Device disabling
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@param[in] DeviceNum Device Number
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@retval TRUE At least one higher function device is enabled
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FALSE Higher functions are disabled
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**/
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BOOLEAN
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SerialIoHigherFunctionsEnabled (
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IN UINT8 DeviceNum
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)
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{
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UINT8 FuncNum;
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//
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// Check all other func devs(1 to 7) status except func 0.
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//
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for (FuncNum = 1; FuncNum <= PCI_MAX_FUNC; FuncNum++) {
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if (PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (DEFAULT_PCI_SEGMENT_NUMBER_PCH,
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DEFAULT_PCI_BUS_NUMBER_PCH,
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DeviceNum,
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FuncNum,
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PCI_DEVICE_ID_OFFSET)
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) != 0xFFFF) {
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return TRUE;
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}
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}
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return FALSE;
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}
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/**
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Places SerialIo device in D3
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@param[in] PciCfgBase Pci Config Offset
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**/
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VOID
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SerialIoSetD3 (
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IN UINT64 PciCfgBase
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)
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{
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if (PciCfgBase < PCH_SERIAL_IO_BASE_ADDRESS) {
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PciSegmentOr32 (PciCfgBase + R_SERIAL_IO_CFG_PME_CTRL_STS, BIT1 | BIT0);
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} else {
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MmioOr8 ((UINTN) PciCfgBase + R_SERIAL_IO_CFG_PME_CTRL_STS, BIT1 | BIT0);
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//
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// Reading back value after write to ensure bridge observes the BAR1 write access
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//
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MmioRead8 ((UINTN) PciCfgBase + R_SERIAL_IO_CFG_PME_CTRL_STS);
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}
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}
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/**
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Places SerialIo device in D0
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@param[in] PciCfgBase Pci Config Offset
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**/
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VOID
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SerialIoSetD0 (
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IN UINT64 PciCfgBase
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)
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{
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if (PciCfgBase < PCH_SERIAL_IO_BASE_ADDRESS) {
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PciSegmentAnd32 ((UINTN) PciCfgBase + R_SERIAL_IO_CFG_PME_CTRL_STS, (UINT32) ~(BIT1 | BIT0));
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} else {
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MmioAnd32 ((UINTN) PciCfgBase + R_SERIAL_IO_CFG_PME_CTRL_STS, (UINT32) ~(BIT1 | BIT0));
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//
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// Reading back value after write to ensure bridge observes the BAR1 write access
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//
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MmioRead32 ((UINTN) PciCfgBase + R_SERIAL_IO_CFG_PME_CTRL_STS);
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}
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}
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/**
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Allows memory access
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@param[in] PciCfgBase Pci Config Offset
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@param[in] Hidden Mode that determines access type
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**/
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VOID
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SerialIoEnableMse (
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IN UINT64 PciCfgBase,
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IN BOOLEAN Hidden
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)
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{
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if (Hidden) {
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MmioOr16 ((UINTN) PciCfgBase + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_MEMORY_SPACE);
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//
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// Reading back value after write to ensure bridge observes the BAR1 write access
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//
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MmioRead16 ((UINTN) PciCfgBase + PCI_COMMAND_OFFSET);
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} else {
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PciSegmentOr16 ((UINTN) PciCfgBase + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_MEMORY_SPACE);
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}
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}
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/**
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Disable SerialIo memory access
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@param[in] PciCfgBase Pci Config Offset
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**/
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VOID
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SerialIoDisableMse (
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IN UINT64 PciCfgBase
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)
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{
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PciSegmentAnd16 ((UINTN) PciCfgBase + PCI_COMMAND_OFFSET, (UINT16) ~EFI_PCI_COMMAND_MEMORY_SPACE);
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}
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/**
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Disable SerialIo memory encoding
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Designated for Pci modes
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@param[in] PciCfgBase Pci Config Offset
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@param[in] RemoveTempBar Remove temporary mem base address or not
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**/
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VOID
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SerialIoMmioDisable (
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IN UINT64 PciCfgBase,
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IN BOOLEAN RemoveBar
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)
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{
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SerialIoDisableMse (PciCfgBase);
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if (RemoveBar == TRUE) {
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PciSegmentWrite32 ((UINTN) PciCfgBase + R_SERIAL_IO_CFG_BAR0_LOW, 0x0);
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PciSegmentWrite32 ((UINTN) PciCfgBase + R_SERIAL_IO_CFG_BAR0_HIGH, 0x0);
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}
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}
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