/** @file
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Device IDs for Serial IO Controllers for TGL PCH
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Conventions:
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- Register definition format:
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Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
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- Prefix:
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Definitions beginning with "R_" are registers
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Definitions beginning with "B_" are bits within registers
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Definitions beginning with "V_" are meaningful values within the bits
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Definitions beginning with "S_" are register size
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Definitions beginning with "N_" are the bit position
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- [GenerationName]:
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Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
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Register name without GenerationName applies to all generations.
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- [ComponentName]:
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This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
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Register name without ComponentName applies to all components.
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Register that is specific to -LP denoted by "_PCH_LP_" in component name.
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- SubsystemName:
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This field indicates the subsystem name of the component that the register belongs to
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(e.g. PCIE, USB, SATA, GPIO, PMC etc.).
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- RegisterSpace:
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MEM - MMIO space register of subsystem.
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IO - IO space register of subsystem.
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PCR - Private configuration register of subsystem.
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CFG - PCI configuration space register of subsystem.
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- RegisterName:
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Full register name.
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Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _SERIAL_IO_REGS_VER2_H_
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#define _SERIAL_IO_REGS_VER2_H_
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//
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// Serial IO I2C0 Controller Registers
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//
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#define V_VER2_PCH_LP_SERIAL_IO_CFG_I2C0_DEVICE_ID 0xA0E8
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//
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// Serial IO I2C1 Controller Registers
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//
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#define V_VER2_PCH_LP_SERIAL_IO_CFG_I2C1_DEVICE_ID 0xA0E9
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//
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// Serial IO I2C2 Controller Registers
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//
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#define V_VER2_PCH_LP_SERIAL_IO_CFG_I2C2_DEVICE_ID 0xA0EA
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//
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// Serial IO I2C3 Controller Registers
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//
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#define V_VER2_PCH_LP_SERIAL_IO_CFG_I2C3_DEVICE_ID 0xA0EB
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//
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// Serial IO I2C4 Controller Registers
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//
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#define V_VER2_PCH_LP_SERIAL_IO_CFG_I2C4_DEVICE_ID 0xA0C5
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//
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// Serial IO I2C5 Controller Registers
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//
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#define V_VER2_PCH_LP_SERIAL_IO_CFG_I2C5_DEVICE_ID 0xA0C6
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//
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// Serial IO SPI0 Controller Registers
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//
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#define V_VER2_PCH_LP_SERIAL_IO_CFG_SPI0_DEVICE_ID 0xA0AA
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//
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// Serial IO SPI1 Controller Registers
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//
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#define V_VER2_PCH_LP_SERIAL_IO_CFG_SPI1_DEVICE_ID 0xA0AB
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//
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// Serial IO SPI2 Controller Registers
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//
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#define V_VER2_PCH_LP_SERIAL_IO_CFG_SPI2_DEVICE_ID 0xA0FB
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//
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// Serial IO SPI3 Controller Registers
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//
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#define V_VER2_PCH_LP_SERIAL_IO_CFG_SPI3_DEVICE_ID 0xA0FD
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//
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// Serial IO UART0 Controller Registers
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//
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#define V_VER2_PCH_LP_SERIAL_IO_CFG_UART0_DEVICE_ID 0xA0A8
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//
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// Serial IO UART1 Controller Registers
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//
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#define V_VER2_PCH_LP_SERIAL_IO_CFG_UART1_DEVICE_ID 0xA0A9
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//
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// Serial IO UART2 Controller Registers
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//
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#define V_VER2_PCH_LP_SERIAL_IO_CFG_UART2_DEVICE_ID 0xA0C7
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//
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// Serial IO UART3 Controller Registers
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//
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#define V_VER2_PCH_LP_SERIAL_IO_CFG_UART3_DEVICE_ID 0xA0DA
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#endif //_SERIAL_IO_REGS_VER2_H_
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