/** @file
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This file contains internal header for PSF lib usage
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Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _PCH_PSF_PRIVATE_LIB_INTERNAL_H_
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#define _PCH_PSF_PRIVATE_LIB_INTERNAL_H_
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#include <Library/PsfLib.h>
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#include <Register/PchPcrRegs.h>
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#define PSF_PORT_NULL ((PSF_PORT){0,0})
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#define PSF_IS_PORT_NULL(PsfPort) ((PsfPort.PsfPid == 0) && (PsfPort.RegBase == 0))
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typedef struct {
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PCH_SBI_PID PsfPid;
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UINT32 RegisterAddress;
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UINT8 Fro;
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} PSF_PORT_RELAXED_ORDERING_CONFIG_REG;
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/**
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Disable bridge (e.g. PCIe Root Port) at PSF level
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@param[in] PsfPort PSF PORT data structure
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**/
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VOID
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PsfDisableBridge (
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IN PSF_PORT PsfPort
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);
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/**
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Disable bridge (e.g. PCIe Root Port) at PSF level in RS3
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@param[in] PsfPort PSF PORT data structure
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**/
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VOID
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PsfRs3DisableBridge (
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IN PSF_PORT PsfPort
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);
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/**
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Check if bridge (e.g. PCIe Root Port) is enabled at PSF level
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@param[in] PsfPort PSF PORT data structure
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@retval TRUE Bridge behind PSF Port is enabled
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FALSE Bridge behind PSF Port is disabled
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**/
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BOOLEAN
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PsfIsBridgeEnabled (
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IN PSF_PORT PsfPort
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);
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/**
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Disable device IOSpace at PSF level
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Method not for bridges (e.g. PCIe Root Port)
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@param[in] PsfPort PSF PORT data structure
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**/
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VOID
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PsfDisableDeviceIoSpace (
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IN PSF_PORT PsfPort
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);
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/**
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Enable device IOSpace at PSF level
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Method not for bridges (e.g. PCIe Root Port)
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@param[in] PsfPort PSF PORT data structure
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**/
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VOID
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PsfEnableDeviceIoSpace (
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IN PSF_PORT PsfPort
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);
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/**
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Disable device Memory Space at PSF level
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Method not for bridges (e.g. PCIe Root Port)
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@param[in] PsfPort PSF PORT data structure
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**/
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VOID
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PsfDisableDeviceMemSpace (
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IN PSF_PORT PsfPort
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);
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/**
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Enable device Memory Space at PSF level
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Method not for bridges (e.g. PCIe Root Port)
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@param[in] PsfPort PSF PORT data structure
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**/
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VOID
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PsfEnableDeviceMemSpace (
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IN PSF_PORT PsfPort
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);
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/**
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Set device BARx address at PSF level
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Method not for bridges (e.g. PCIe Root Port)
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@param[in] PsfPort PSF PORT data structure
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@param[in] BarNum BAR Number (0:BAR0, 1:BAR1, ...)
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@param[in] BarValue 32bit BAR value
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**/
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VOID
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PsfSetDeviceBarValue (
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IN PSF_PORT PsfPort,
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IN UINT8 BarNum,
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IN UINT32 BarValue
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);
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/**
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Return PSF_PORT for TraceHub device
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@retval PsfPort PSF PORT structure for TraceHub device
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**/
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PSF_PORT
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PsfTraceHubPort (
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VOID
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);
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/**
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This procedure will return PSF_PORT for TraceHub ACPI device
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@retval PsfPort PSF PORT structure for TraceHub ACPI device
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**/
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PSF_PORT
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PsfTraceHubAcpiDevPort (
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VOID
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);
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/**
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This procedure will return PSF_PORT for SOL device
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@retval PsfPort PSF PORT structure for SOL device
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**/
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PSF_PORT
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PsfSolPort (
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VOID
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);
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/**
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Return PSF_PORT for ISH device
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@retval PsfPort PSF PORT structure for ISH device
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**/
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PSF_PORT
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PsfIshPort (
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VOID
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);
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/**
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Return PSF_PORT for FPAK device
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@retval PsfPort PSF PORT structure for FPAK device
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**/
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PSF_PORT
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PsfFpakPort (
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VOID
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);
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/**
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Return PSF_PORT for CNVi device
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@retval PsfPort PSF PORT structure for CNVi device
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**/
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PSF_PORT
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PsfCnviPort (
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VOID
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);
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/**
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Return PSF_PORT for PMC device
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@retval PsfPort PSF PORT structure for PMC device
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**/
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PSF_PORT
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PsfPmcPort (
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VOID
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);
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/**
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Return second level PSF_PORT to which PCIE Root Port device is connected (directly)
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@param[in] RpIndex PCIe Root Port Index (0 based)
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@retval PsfPort PSF PORT structure for PCIe
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**/
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PSF_PORT
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PsfPcieSecondLevelPort (
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IN UINT32 RpIndex
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);
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/**
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Return PSF_PORT at root PSF level to which PCIe Root Port device is connected
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@param[in] RpIndex PCIe Root Port Index (0 based)
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@retval PsfPort PSF PORT structure for PCIe
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**/
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PSF_PORT
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PsfRootPciePort (
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IN UINT32 RpIndex
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);
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/**
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Return RS3 PSF_PORT at root PSF level to which PCIe Root Port device is connected
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@param[in] RpIndex PCIe Root Port Index (0 based)
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@retval PsfPort PSF PORT structure for PCIe
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**/
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PSF_PORT
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PsfRootRs3PciePort (
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IN UINT32 RpIndex
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);
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/**
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Check if PCIe Root Port is enabled
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@param[in] RpIndex PCIe Root Port Index (0 based)
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@retval TRUE PCIe Root Port is enabled
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FALSE PCIe Root Port is disabled
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**/
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BOOLEAN
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PsfIsPcieRootPortEnabled (
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IN UINT32 RpIndex
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);
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//
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// Type of enpoint connected to PSF port.
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// PsfNullPort is used for ports which do not exist
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//
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typedef enum {
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PsfNullPort,
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PsfToPsfPort,
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PsfPcieCtrlPort
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} PSF_TOPO_PORT_TYPE;
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//
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// Structure for storing information on location in PSF topology
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// Every PSF node is identified by PsfID and PsfPortId
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//
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typedef struct {
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UINT8 PsfId;
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UINT8 PortId;
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} PSF_TOPO_PORT;
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#define PSF_TOPO_PORT_NULL ((PSF_TOPO_PORT){0, 0})
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#define PSF_IS_TOPO_PORT_NULL(PsfTopoPort) (((PsfTopoPort).PsfId == 0) && ((PsfTopoPort).PortId == 0))
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//
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// This is optional field containing PSF port specific data
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//
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typedef union {
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UINT32 PcieCtrlIndex;
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} PSF_TOPO_PORT_DATA;
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//
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// Structure representing PSF port in PSF topology
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// If port is of PsfToPsfPort type Child will point to the first
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// port of sub PSF segment.
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//
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typedef struct PSF_TOPOLOGY {
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PSF_TOPO_PORT PsfPort;
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PSF_TOPO_PORT_TYPE PortType;
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CONST struct PSF_TOPOLOGY *Child;
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PSF_TOPO_PORT_DATA PortData;
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} PSF_TOPOLOGY;
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//
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// Tag for identifying last element of PSF_TOPOLOGY type array
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//
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#define PSF_TOPOLOGY_END {{0, 0}, PsfNullPort, NULL}
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/**
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Get PSF Pcie Tree topology
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@param[in] PsfTopology PSF Port from PSF PCIe tree topology
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@retval PsfTopology PSF PCIe tree topology
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**/
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CONST PSF_TOPOLOGY*
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PsfGetRootPciePsfTopology (
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VOID
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);
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//
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// Structure for storing data on PCIe controller to PSF assignment and GrantCount register offsets
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//
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typedef struct {
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PCH_SBI_PID PsfPid;
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UINT16 DevGntCnt0Base;
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UINT16 TargetGntCntPg1Tgt0Base;
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} PSF_GRANT_COUNT_REG;
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/**
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Grant count regs data for PSF that is directly connected to PCIe Root Ports
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@param[in] Controller PCIe Root Port Controller index (0 based)
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@param[out] GrantCountReg Structure with PSF Grant Count register data
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**/
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VOID
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PsfPcieGrantCountBaseReg (
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IN UINT8 Controller,
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OUT PSF_GRANT_COUNT_REG *GrantCountReg
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);
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/**
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Get Grant Count number (Device Grant Count and Target Grant Count)
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for PSF that is directly connected to PCIe Root Ports
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@param[in] Controller PCIe Root Port Controller index
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@param[in] Channel PCIe Root Port Channel index
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@param[out] DgcrNo Device Grant Count number
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@param[out] PgTgtNo Target Grant Count number
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**/
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VOID
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PsfPcieGrantCountNumber (
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IN UINT8 Controller,
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IN UINT8 Channel,
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OUT UINT8 *DgcrNo,
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OUT UINT8 *PgTgtNo
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);
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/**
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Grant count regs data for a given PSF-to-PSF port.
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@param[in] PsfTopoPort PSF-to-PSF port
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@param[out] GrantCountReg Structure with PSF Grant Count register data
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**/
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VOID
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PsfSegmentGrantCountBaseReg (
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IN PSF_TOPO_PORT PsfTopoPort,
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OUT PSF_GRANT_COUNT_REG *GrantCountReg
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);
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/**
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Grant Count number (Device Grant Count and Target Grant Count) for a given PSF-to-PSF port.
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@param[in] PsfTopoPort PSF-to-PSF port
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@param[out] DgcrNo Device Grant Count number
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@param[out] PgTgtNo Target Grant Count number
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**/
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VOID
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PsfSegmentGrantCountNumber (
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IN PSF_TOPO_PORT PsfTopoPort,
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OUT UINT8 *DgcrNo,
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OUT UINT8 *PgTgtNo
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);
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//
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// Do not override PSF Grant Count value and leave HW default setting
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//
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#define DEFAULT_PCIE_GRANT_COUNT 0xFF
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/**
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Get PSF SideBand Port ID from PSF ID (1 - PSF1, 2 - PSF2, ...)
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@param[in] PsfId PSF ID (1 - PSF1, 2 - PSF2, ...)
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@retval PSF SideBand Port ID
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**/
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PCH_SBI_PID
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PsfSbPortId (
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UINT32 PsfId
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);
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/**
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Get EOI register data for given PSF ID
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@param[in] PsfId PSF ID (1 - PSF1, 2 - PSF2, ...)
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@param[out] EoiTargetBase EOI Target register
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@param[out] EoiControlBase EOI Control register
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@retval MaxTargets Number of supported targets
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**/
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UINT8
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PsfEoiRegData (
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UINT32 PsfId,
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UINT16 *EoiTargetBase,
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UINT16 *EoiControlBase
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);
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/**
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Get MCTP register data for given PSF ID
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@param[in] PsfId PSF ID (1 - PSF1, 2 - PSF2, ...)
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@param[out] MctpTargetBase MCTP Target register
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@param[out] MctpControlBase MCTP Control register
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@retval MaxTargets Number of supported targets
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**/
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UINT8
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PsfMctpRegData (
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UINT32 PsfId,
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UINT16 *MctpTargetBase,
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UINT16 *MctpControlBase
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);
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/**
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Check if MCTP is supported
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@retval TRUE MCTP is supported
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FALSE MCTP is not supported
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**/
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BOOLEAN
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PsfIsMctpSupported (
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VOID
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);
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/**
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Return the PSF (Root level) Function Config PSF_PORT for PCIe Root Port
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@param[in] RpIndex PCIe Root Port Index (0 based)
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@retval PsfPort PSF PORT structure for PCIe Function Config
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**/
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PSF_PORT
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PsfRootPcieFunctionConfigPort (
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IN UINT32 RpIndex
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);
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/**
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Return the PSF (Root level) RS3 Function Config PSF_PORT for PCIe Root Port
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@param[in] RpIndex PCIe Root Port Index (0 based)
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@retval PsfPort PSF PORT structure for PCIe Function Config
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**/
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PSF_PORT
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PsfRootRs3PcieFunctionConfigPort (
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IN UINT32 RpIndex
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);
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/**
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Return the PSF Function Config Second Level PSF_PORT for PCIe Root Port
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@param[in] RpIndex PCIe Root Port Index (0 based)
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@retval PsfPort PSF PORT structure for PCIe Function Config
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**/
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PSF_PORT
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PsfPcieFunctionConfigSecondLevelPort (
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IN UINT32 RpIndex
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);
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/**
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This function returns Psf Port Relaxed Ordering Configs
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@param[out] PsfPortRelaxedOrderingConfigRegs PCH Series specific table
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@param[out] PsfPortRelaxedOrderingConfigRegsTableSize PCH Series specific table size
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@param[out] PsfPortRelaxedOrderingConfigRegsPchTypeSpecific PCH type specific table
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@param[out] PsfPortRelaxedOrderingConfigRegsPchTypeSpecificTableSize PCH type specific table size
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**/
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VOID
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GetPsfPortRelaxedOrderingTables (
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PSF_PORT_RELAXED_ORDERING_CONFIG_REG** PsfPortRelaxedOrderingConfigRegs,
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UINT32* PsfPortRelaxedOrderingConfigRegsTableSize,
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PSF_PORT_RELAXED_ORDERING_CONFIG_REG** PsfPortRelaxedOrderingConfigRegsPchTypeSpecific,
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UINT32* PsfPortRelaxedOrderingConfigRegsPchTypeSpecificTableSize
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);
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#endif
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