/** @file
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PCIE root port library.
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All function in this library is available for PEI, DXE, and SMM,
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But do not support UEFI RUNTIME environment call.
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Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Base.h>
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#include <Uefi/UefiBaseType.h>
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#include <Library/IoLib.h>
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#include <Library/DebugLib.h>
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#include <Library/BaseLib.h>
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#include <Library/PciSegmentLib.h>
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#include <Library/PchInfoLib.h>
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#include <Library/PchPcrLib.h>
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#include <Library/PchPcieRpLib.h>
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#include <PcieRegs.h>
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#include <Register/PchRegs.h>
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#include <PchPcieRpInfo.h>
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#include <Register/PchPcieRpRegs.h>
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#include <Register/PchPcrRegs.h>
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#include <Library/PchPciBdfLib.h>
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#include "PchPcieRpLibInternal.h"
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/**
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Gets pci segment base address of PCIe root port.
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@param RpIndex Root Port Index (0 based)
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@return PCIe port base address.
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**/
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UINT64
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PchPcieBase (
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IN UINT32 RpIndex
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)
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{
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return PchPcieRpPciCfgBase (RpIndex);
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}
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/**
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Determines whether L0s is supported on current stepping.
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@return TRUE if L0s is supported, FALSE otherwise
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**/
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BOOLEAN
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PchIsPcieL0sSupported (
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VOID
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)
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{
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return TRUE;
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}
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/**
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Some early PCH steppings require Native ASPM to be disabled due to hardware issues:
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- RxL0s exit causes recovery
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- Disabling PCIe L0s capability disables L1
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Use this function to determine affected steppings.
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@return TRUE if Native ASPM is supported, FALSE otherwise
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**/
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BOOLEAN
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PchIsPcieNativeAspmSupported (
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VOID
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)
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{
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return PchIsPcieL0sSupported ();
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}
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