/** @file
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This file contains routines that support PCI Express initialization
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Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Library/PcieHelperLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <PcieRegs.h>
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#define ASPM_L1_NO_LIMIT 0xFF
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#define LINK_RETRAIN_WAIT_TIME 1000 // microseconds
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/**
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Finds the Offset to a given Capabilities ID
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Each capability has an ID and a pointer to next Capability, so they form a linked list.
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This function walks the list of Capabilities present in device's pci cfg. If requested capability
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can be found, its offset is returned.
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If the capability can't be found or if device doesn't exist, function returns 0
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CAPID list:
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0x01 = PCI Power Management Interface
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0x04 = Slot Identification
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0x05 = MSI Capability
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0x10 = PCI Express Capability
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@param[in] DeviceBase device's base address
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@param[in] CapId CAPID to search for
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@retval 0 CAPID not found (this includes situation where device doesn't exit)
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@retval Other CAPID found, Offset of desired CAPID
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**/
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UINT8
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PcieBaseFindCapId (
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IN UINT64 DeviceBase,
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IN UINT8 CapId
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)
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{
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UINT8 CapHeaderOffset;
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UINT8 CapHeaderId;
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UINT16 Data16;
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//
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// We do not explicitly check if device exists to save time and avoid unnecessary PCI access
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// If the device doesn't exist, check for CapHeaderId != 0xFF will fail and function will return offset 0
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//
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if ((PciSegmentRead8 (DeviceBase + PCI_PRIMARY_STATUS_OFFSET) & EFI_PCI_STATUS_CAPABILITY) == 0x00) {
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///
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/// Function has no capability pointer
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///
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return 0;
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} else {
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///
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/// Check the header layout to determine the Offset of Capabilities Pointer Register
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///
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if ((PciSegmentRead8 (DeviceBase + PCI_HEADER_TYPE_OFFSET) & HEADER_LAYOUT_CODE) == (HEADER_TYPE_CARDBUS_BRIDGE)) {
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///
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/// If CardBus bridge, start at Offset 0x14
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///
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CapHeaderOffset = EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR;
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} else {
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///
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/// Otherwise, start at Offset 0x34
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///
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CapHeaderOffset = PCI_CAPBILITY_POINTER_OFFSET;
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}
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///
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/// Get Capability Header, A pointer value of 00h is used to indicate the last capability in the list.
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///
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CapHeaderId = 0;
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CapHeaderOffset = PciSegmentRead8 (DeviceBase + CapHeaderOffset) & ((UINT8) ~(BIT0 | BIT1));
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while (CapHeaderOffset != 0 && CapHeaderId != 0xFF) {
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Data16 = PciSegmentRead16 (DeviceBase + CapHeaderOffset);
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CapHeaderId = (UINT8)(Data16 & 0xFF);
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if (CapHeaderId == CapId) {
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if (CapHeaderOffset > PCI_MAXLAT_OFFSET) {
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///
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/// Return valid capability offset
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///
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return CapHeaderOffset;
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} else {
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ASSERT ((FALSE));
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return 0;
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}
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}
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///
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/// Each capability must be DWORD aligned.
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/// The bottom two bits of all pointers (including the initial pointer at 34h) are reserved
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/// and must be implemented as 00b although software must mask them to allow for future uses of these bits.
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///
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CapHeaderOffset = (UINT8)(Data16 >> 8);
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}
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return 0;
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}
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}
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/**
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Find the Offset to a given Capabilities ID
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CAPID list:
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0x01 = PCI Power Management Interface
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0x04 = Slot Identification
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0x05 = MSI Capability
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0x10 = PCI Express Capability
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@param[in] Segment Pci Segment Number
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@param[in] Bus Pci Bus Number
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@param[in] Device Pci Device Number
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@param[in] Function Pci Function Number
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@param[in] CapId CAPID to search for
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@retval 0 CAPID not found
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@retval Other CAPID found, Offset of desired CAPID
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**/
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UINT8
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PcieFindCapId (
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IN UINT8 Segment,
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IN UINT8 Bus,
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IN UINT8 Device,
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IN UINT8 Function,
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IN UINT8 CapId
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)
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{
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UINT64 DeviceBase;
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DeviceBase = PCI_SEGMENT_LIB_ADDRESS (Segment, Bus, Device, Function, 0);
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return PcieBaseFindCapId (DeviceBase, CapId);
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}
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/**
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Search and return the offset of desired Pci Express Capability ID
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CAPID list:
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0x0001 = Advanced Error Reporting Capability
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0x0002 = Virtual Channel Capability
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0x0003 = Device Serial Number Capability
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0x0004 = Power Budgeting Capability
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@param[in] DeviceBase device base address
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@param[in] CapId Extended CAPID to search for
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@retval 0 CAPID not found, this includes situation where device doesn't exist
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@retval Other CAPID found, Offset of desired CAPID
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**/
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UINT16
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PcieBaseFindExtendedCapId (
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IN UINT64 DeviceBase,
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IN UINT16 CapId
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)
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{
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UINT16 CapHeaderOffset;
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UINT16 CapHeaderId;
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///
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/// Start to search at Offset 0x100
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/// Get Capability Header, A pointer value of 00h is used to indicate the last capability in the list.
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///
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CapHeaderId = 0;
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CapHeaderOffset = R_PCIE_CFG_EXCAP_OFFSET;
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while (CapHeaderOffset != 0 && CapHeaderId != MAX_UINT16) {
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CapHeaderId = PciSegmentRead16 (DeviceBase + CapHeaderOffset);
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if (CapHeaderId == CapId) {
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return CapHeaderOffset;
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}
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///
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/// Each capability must be DWORD aligned.
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/// The bottom two bits of all pointers are reserved and must be implemented as 00b
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/// although software must mask them to allow for future uses of these bits.
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///
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CapHeaderOffset = (PciSegmentRead16 (DeviceBase + CapHeaderOffset + 2) >> 4) & ((UINT16) ~(BIT0 | BIT1));
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}
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return 0;
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}
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/**
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Search and return the offset of desired Pci Express Capability ID
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CAPID list:
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0x0001 = Advanced Error Reporting Capability
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0x0002 = Virtual Channel Capability
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0x0003 = Device Serial Number Capability
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0x0004 = Power Budgeting Capability
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@param[in] Segment Pci Segment Number
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@param[in] Bus Pci Bus Number
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@param[in] Device Pci Device Number
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@param[in] Function Pci Function Number
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@param[in] CapId Extended CAPID to search for
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@retval 0 CAPID not found, this includes situation where device doesn't exist
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@retval Other CAPID found, Offset of desired CAPID
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**/
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UINT16
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PcieFindExtendedCapId (
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IN UINT8 Segment,
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IN UINT8 Bus,
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IN UINT8 Device,
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IN UINT8 Function,
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IN UINT16 CapId
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)
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{
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UINT64 DeviceBase;
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DeviceBase = PCI_SEGMENT_LIB_ADDRESS (Segment, Bus, Device, Function, 0);
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return PcieBaseFindExtendedCapId (DeviceBase, CapId);
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}
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/**
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Checks if PCI device at given address exists
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@param[in] Base device's base address
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@retval TRUE if exists
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**/
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BOOLEAN
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IsDevicePresent (
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UINT64 Base
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)
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{
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if (PciSegmentRead16 (Base) == 0xFFFF) {
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return FALSE;
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}
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return TRUE;
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}
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/**
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Checks if device is a multifunction device
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Besides comparing Multifunction bit (BIT7) it checks if contents of HEADER_TYPE register
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make sense (header != 0xFF) to prevent false positives when called on devices which do not exist
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@param[in] Base device's base address
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@retval TRUE if multifunction; FALSE otherwise
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**/
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BOOLEAN
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IsMultifunctionDevice (
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UINT64 Base
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)
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{
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UINT8 HeaderType;
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HeaderType = PciSegmentRead8(Base + PCI_HEADER_TYPE_OFFSET);
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if ((HeaderType == 0xFF) || ((HeaderType & HEADER_TYPE_MULTI_FUNCTION) == 0)) {
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return FALSE;
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}
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return TRUE;
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}
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/**
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Checks device's Slot Clock Configuration
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@param[in] Base device's base address
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@param[in] PcieCapOffset devices Pci express capability list register offset
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@retval TRUE when device uses slot clock, FALSE otherwise
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**/
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BOOLEAN
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GetScc (
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UINT64 Base,
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UINT8 PcieCapOffset
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)
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{
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return !!(PciSegmentRead16 (Base + PcieCapOffset + R_PCIE_LSTS_OFFSET) & B_PCIE_LSTS_SCC);
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}
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/**
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Sets Common Clock Configuration bit for given device.
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@param[in] PcieCapOffset devices Pci express capability list register offset
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@param[in] Base device's base address
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**/
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VOID
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EnableCcc (
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UINT64 Base,
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UINT8 PcieCapOffset
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)
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{
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PciSegmentOr8 (Base + PcieCapOffset + R_PCIE_LCTL_OFFSET, B_PCIE_LCTL_CCC);
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}
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/**
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Retrains link behind given device.
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It only makes sense to call it for downstream ports. If called for upstream port nothing will happen.
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If WaitUntilDone is TRUE function will wait until link retrain had finished, otherwise it will return immediately.
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Link must finish retrain before software can access the device on the other side. If it's not going to access it
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then considerable time can be saved by not waiting here.
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@param[in] Base device's base address
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@param[in] PcieCapOffset devices Pci express capability list register offset
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@param[in] WaitUntilDone when TRUE, function waits until link has retrained
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**/
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VOID
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RetrainLink (
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UINT64 Base,
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UINT8 PcieCapOffset,
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BOOLEAN WaitUntilDone
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)
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{
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UINT16 LinkTraining;
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UINT32 TimeoutUs;
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TimeoutUs = LINK_RETRAIN_WAIT_TIME;
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//
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// Before triggering link retrain make sure it's not already retraining. Otherwise
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// settings recently entered in LCTL register might go unnoticed
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//
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do {
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LinkTraining = (PciSegmentRead16 (Base + PcieCapOffset + R_PCIE_LSTS_OFFSET) & B_PCIE_LSTS_LT);
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TimeoutUs--;
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} while (LinkTraining && (TimeoutUs != 0));
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PciSegmentOr8 (Base + PcieCapOffset + R_PCIE_LCTL_OFFSET, B_PCIE_LCTL_RL);
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TimeoutUs = LINK_RETRAIN_WAIT_TIME;
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if (WaitUntilDone) {
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do {
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LinkTraining = (PciSegmentRead16 (Base + PcieCapOffset + R_PCIE_LSTS_OFFSET) & B_PCIE_LSTS_LT);
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TimeoutUs--;
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} while (LinkTraining && (TimeoutUs != 0));
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}
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}
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