/** @file
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Register names for GbE device
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Conventions:
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- Register definition format:
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Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
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- Prefix:
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Definitions beginning with "R_" are registers
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Definitions beginning with "B_" are bits within registers
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Definitions beginning with "V_" are meaningful values within the bits
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Definitions beginning with "S_" are register size
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Definitions beginning with "N_" are the bit position
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- [GenerationName]:
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Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
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Register name without GenerationName applies to all generations.
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- [ComponentName]:
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This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
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Register name without ComponentName applies to all components.
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Register that is specific to -LP denoted by "_PCH_LP_" in component name.
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- SubsystemName:
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This field indicates the subsystem name of the component that the register belongs to
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(e.g. PCIE, USB, SATA, GPIO, PMC etc.).
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- RegisterSpace:
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MEM - MMIO space register of subsystem.
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IO - IO space register of subsystem.
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PCR - Private configuration register of subsystem.
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CFG - PCI configuration space register of subsystem.
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- RegisterName:
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Full register name.
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Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _GBE_REGS_H_
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#define _GBE_REGS_H_
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#define R_GBE_CFG_MBARA 0x10
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#define N_GBE_CFG_MBARA_ALIGN 17
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#define R_GBE_CFG_PMCS 0xCC
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#define B_GBE_CFG_PMCS_PS (BIT1 | BIT0)
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#define V_GBE_CFG_PMCS_PS0 0x00
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//
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// Gigabit Ethernet LAN Capabilities and Status Registers (Memory space)
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//
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#define R_GBE_MEM_CSR_CTRL 0
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//
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// LANPHYPC:
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// Connects to the LCD DEVICE_OFF# signal in the
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// LAN Connected Device
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//
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#define B_GBE_MEM_CSR_CTRL_LANPHYPC_OVERRIDE BIT16 // When set to 1 SW driver has the ability to control the LANPHYPC pin value.
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#define B_GBE_MEM_CSR_CTRL_LANPHYPC_VAL BIT17 // When set to 1 this bit will define the value of the LANPHYPC pin.
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#define R_GBE_MEM_CSR_CTRL_EXT 0x0018
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#define B_GBE_MEM_CSR_CTRL_EXT_LPCD BIT2 //LCD Power Cycle Done (LPCD). This bit indicates whether LCD power cycle is done
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//- the bit is set 50/100mSec after LANPHYPC pin assertion.
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#define B_GBE_MEM_CSR_CTRL_EXT_FORCE_SMB BIT11
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#define R_GBE_MEM_CSR_MDIC 0x0020
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#define B_GBE_MEM_CSR_MDIC_RB BIT28
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#define R_GBE_MEM_CSR_EXTCNF_CTRL 0x0F00
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#define B_GBE_MEM_CSR_EXTCNF_CTRL_SWFLAG BIT5
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#define R_GBE_MEM_CSR_RAL 0x5400
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#define R_GBE_MEM_CSR_RAH 0x5404
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#define B_GBE_MEM_CSR_RAH_RAH 0x0000FFFF
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#define R_GBE_MEM_CSR_WUC 0x5800
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#define B_GBE_MEM_CSR_WUC_APME BIT0
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#endif
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