/** @file
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This file contains definitions of PCIe controller information
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Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _CPU_PCIE_INFO_H_
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#define _CPU_PCIE_INFO_H_
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#define PCIE_HWEQ_COEFFS_MAX 5
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//
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// Device 1 Memory Mapped IO Register Offset Equates
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//
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#define SA_PEG_DEV_NUM 0x01
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#define SA_PEG0_DEV_NUM SA_PEG_DEV_NUM
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#define SA_PEG3_DEV_NUM 0x06
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//
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// SA PCI Express* Port configuration
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//
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#define CPU_PCIE_MAX_ROOT_PORTS 4
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#define SA_PEG_MAX_FUN 0x04
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#define SA_PEG_MAX_LANE 0x14
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#define SA_PEG_MAX_FUN_GEN3 0x03
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#define SA_PEG_MAX_LANE_GEN3 0x10
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#define SA_PEG_MAX_BUNDLE_GEN3 0x08
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#endif
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