/** @file
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Serial IO policy
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Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _SERIAL_IO_DEVICES_H_
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#define _SERIAL_IO_DEVICES_H_
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#include <Protocol/SerialIo.h>
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#include <PchLimits.h>
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#pragma pack (push,1)
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/**
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Available working modes for SerialIo SPI Host Controller
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0: SerialIoSpiDisabled;
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- Device is placed in D3
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- Gpio configuration is skipped
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- PSF:
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!important! If given device is Function 0 and other higher functions on given device
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are enabled, PSF disabling is skipped. PSF default will remain and device PCI CFG Space will still be visible.
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This is needed to allow PCI enumerator access functions above 0 in a multifunction device.
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<b>1: SerialIoSpiPci;</b>
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- Gpio pin configuration in native mode for each assigned pin
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- Device will be enabled in PSF
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- Only BAR0 will be enabled
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2: SerialIoSpiHidden;
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- Gpio pin configuration in native mode for each assigned pin
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- Device disabled in the PSF
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- Both BARs are enabled, BAR1 becomes devices Pci Config Space
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- BAR0 assigned from the global PCH reserved memory range, reported as motherboard resource by SIRC
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@note
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If this controller is located at function 0 and it's mode is set to hidden it will not be visible in the PCI space.
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**/
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typedef enum {
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SerialIoSpiDisabled,
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SerialIoSpiPci,
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SerialIoSpiHidden
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} SERIAL_IO_SPI_MODE;
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/**
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Used to set Inactive/Idle polarity of Spi Chip Select
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**/
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typedef enum {
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SerialIoSpiCsActiveLow = 0,
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SerialIoSpiCsActiveHigh = 1
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} SERIAL_IO_CS_POLARITY;
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/**
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The SERIAL_IO_SPI_CONFIG provides the configurations to set the Serial IO SPI controller
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**/
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typedef struct {
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UINT8 Mode; ///< <b>SerialIoSpiPci </b> see SERIAL_IO_SPI_MODE
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UINT8 DefaultCsOutput; ///< <b>0 = CS0</b> CS1, CS2, CS3. Default CS used by the SPI HC
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UINT8 CsPolarity[PCH_MAX_SERIALIO_SPI_CHIP_SELECTS]; ///< Selects SPI ChipSelect signal polarity, 0 = low <b>1 = High</b>
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UINT8 CsEnable[PCH_MAX_SERIALIO_SPI_CHIP_SELECTS]; ///< <b>0 = Enable</b> 1 = Disable. Based on this setting GPIO for given SPIx CSx will be configured in Native mode
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UINT8 CsMode; ///< <b>0 = HW Control</b> 1 = SW Control. Sets Chip Select Control mode Hardware or Software.
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UINT8 CsState; ///< <b>0 = CS is set to low</b> 1 = CS is set to high
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} SERIAL_IO_SPI_CONFIG;
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/**
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Available working modes for SerialIo UART Host Controller
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0: SerialIoUartDisabled;
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- Device is placed in D3
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- Gpio configuration is skipped
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- PSF:
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!important! If given device is Function 0 and other higher functions on given device
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are enabled, PSF disabling is skipped. PSF default will remain and device PCI CFG Space will still be visible.
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This is needed to allow PCI enumerator access functions above 0 in a multifunction device.
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<b>1: SerialIoUartPci;</b>
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- Designated for Serial IO UART OS driver usage
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- Gpio pin configuration in native mode for each assigned pin
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- Device will be enabled in PSF
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- Only BAR0 will be enabled
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2: SerialIoUartHidden;
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- Designated for BIOS and/or DBG2 OS kernel debug
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- Gpio pin configuration in native mode for each assigned pin
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- Device disabled in the PSF
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- Both BARs are enabled, BAR1 becomes devices Pci Config Space
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- BAR0 assigned from the global PCH reserved memory range, reported as motherboard resource by SIRC
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@note
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If this controller is located at function 0 and it's mode is set to hidden it will not be visible in the PCI space.
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3: SerialIoUartCom;
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- Designated for 16550/PNP0501 compatible COM device
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- Gpio pin configuration in native mode for each assigned pin
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- Device disabled in the PSF
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- Both BARs are enabled, BAR1 becomes devices Pci Config Space
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- BAR0 assigned from the global PCH reserved memory range, reported as motherboard resource by SIRC
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4: SerialIoUartSkipInit;
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- Gpio configuration is skipped
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- PSF configuration is skipped
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- BAR assignemnt is skipped
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- D-satate setting is skipped
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**/
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typedef enum {
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SerialIoUartDisabled,
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SerialIoUartPci,
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SerialIoUartHidden,
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SerialIoUartCom,
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SerialIoUartSkipInit
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} SERIAL_IO_UART_MODE;
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/**
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UART Settings
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**/
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typedef struct {
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UINT32 BaudRate; ///< <b> 115200 </b> Max 6000000 MdePkg.dec PcdUartDefaultBaudRate
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UINT8 Parity; ///< <b> 1 - No Parity</b> see EFI_PARITY_TYPE MdePkg.dec PcdUartDefaultParity
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UINT8 DataBits; ///< <b>8</b> MdePkg.dec PcdUartDefaultDataBits
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UINT8 StopBits; ///< <b>1 - One Stop Bit</b> see EFI_STOP_BITS_TYPE MdePkg.dec PcdUartDefaultStopBits
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UINT8 AutoFlow; ///< <b>FALSE</b> IntelFrameworkModulePkg.dsc PcdIsaBusSerialUseHalfHandshake
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} SERIAL_IO_UART_ATTRIBUTES;
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/**
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UART signals pin muxing settings. If signal can be enable only on a single pin
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then this parameter is ignored by RC. Refer to GPIO_*_MUXING_SERIALIO_UARTx_* in GpioPins*.h
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for supported settings on a given platform
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**/
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typedef struct {
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UINT32 Rx; ///< RXD Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RXD_*
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UINT32 Tx; ///< TXD Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_UARTx_TXD_*
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UINT32 Rts; ///< RTS Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS_*
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UINT32 Cts; ///< CTS Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS_*
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} UART_PIN_MUX;
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/**
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Serial IO UART Controller Configuration
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**/
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typedef struct {
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SERIAL_IO_UART_ATTRIBUTES Attributes; ///< see SERIAL_IO_UART_ATTRIBUTES
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UART_PIN_MUX PinMux; ///< UART pin mux configuration
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UINT8 Mode; ///< <b> SerialIoUartPci </b> see SERIAL_IO_UART_MODE
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UINT8 DBG2; ///< <b> FALSE </b> If TRUE adds UART to DBG2 table and overrides UartPg to SerialIoUartPgDisabled
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UINT8 PowerGating; ///< <b> SerialIoUartPgAuto </b> Applies to Hidden/COM/SkipInit see SERIAL_IO_UART_PG
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UINT8 DmaEnable; ///< <b> TRUE </b> Applies to SerialIoUartPci only. Informs OS driver to use DMA, if false it will run in PIO mode
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} SERIAL_IO_UART_CONFIG;
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typedef enum {
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SerialIoUartPgDisabled, ///< No _PS0/_PS3 support, device left in D0, after initialization
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/**
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In mode: SerialIoUartCom;
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_PS0/_PS3 that supports getting device out of reset
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In mode: SerialIoUartPci
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Keeps UART in D0 and assigns Fixed MMIO for SEC/PEI usage only
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**/
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SerialIoUartPgEnabled,
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SerialIoUartPgAuto ///< _PS0 and _PS3, detection through ACPI if device was initialized prior to first PG. If it was used (DBG2) PG is disabled,
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} SERIAL_IO_UART_PG;
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/**
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Available working modes for SerialIo I2C Host Controller
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0: SerialIoI2cDisabled;
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- Device is placed in D3
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- Gpio configuration is skipped
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- PSF:
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!important! If given device is Function 0 and other higher functions on given device
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are enabled, PSF disabling is skipped. PSF default will remain and device PCI CFG Space will still be visible.
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This is needed to allow PCI enumerator access functions above 0 in a multifunction device.
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<b>1: SerialIoI2cPci;</b>
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- Gpio pin configuration in native mode for each assigned pin
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- Device will be enabled in PSF
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- Only BAR0 will be enabled
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2: SerialIoI2cHidden;
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- Gpio pin configuration in native mode for each assigned pin
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- Device disabled in the PSF
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- Both BARs are enabled, BAR1 becomes devices Pci Config Space
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- BAR0 assigned from the global PCH reserved memory range, reported as motherboard resource by SIRC
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@note
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If this controller is located at function 0 and it's mode is set to hidden it will not be visible in the PCI space.
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**/
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typedef enum {
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SerialIoI2cDisabled,
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SerialIoI2cPci,
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SerialIoI2cHidden
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} SERIAL_IO_I2C_MODE;
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/**
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I2C signals pin muxing settings. If signal can be enable only on a single pin
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then this parameter is ignored by RC. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_* in GpioPins*.h
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for supported settings on a given platform
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**/
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typedef struct {
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UINT32 Sda; ///< SDA Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SDA_*
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UINT32 Scl; ///< SCL Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SCL_*
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} I2C_PIN_MUX;
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/**
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Serial IO I2C Controller Configuration
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**/
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typedef struct {
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UINT8 Mode; /// <b>SerialIoI2cPci <b> see SERIAL_IO_I2C_MODE
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/**
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I2C Pads Internal Termination.
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For more information please see Platform Design Guide.
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Supported values (check GPIO_ELECTRICAL_CONFIG for reference):
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<b>GpioTermNone: No termination</b>,
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GpioTermWpu1K: 1kOhm weak pull-up,
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GpioTermWpu5K: 5kOhm weak pull-up,
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GpioTermWpu20K: 20kOhm weak pull-up
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**/
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UINT8 PadTermination;
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UINT8 Reserved[2];
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I2C_PIN_MUX PinMux; ///< I2C pin mux configuration
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} SERIAL_IO_I2C_CONFIG;
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#pragma pack (pop)
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#endif // _SERIAL_IO_DEVICES_H_
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