/** @file
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Register names for PCH PMC device
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Conventions:
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- Register definition format:
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Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
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- Prefix:
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Definitions beginning with "R_" are registers
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Definitions beginning with "B_" are bits within registers
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Definitions beginning with "V_" are meaningful values within the bits
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Definitions beginning with "S_" are register size
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Definitions beginning with "N_" are the bit position
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- [GenerationName]:
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Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
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Register name without GenerationName applies to all generations.
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- [ComponentName]:
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This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
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Register name without ComponentName applies to all components.
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Register that is specific to -LP denoted by "_PCH_LP_" in component name.
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- SubsystemName:
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This field indicates the subsystem name of the component that the register belongs to
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(e.g. PCIE, USB, SATA, GPIO, PMC etc.).
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- RegisterSpace:
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MEM - MMIO space register of subsystem.
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IO - IO space register of subsystem.
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PCR - Private configuration register of subsystem.
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CFG - PCI configuration space register of subsystem.
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- RegisterName:
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Full register name.
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Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _PCH_REGS_PMC_H_
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#define _PCH_REGS_PMC_H_
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//
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// ACPI and legacy I/O register offsets from ACPIBASE
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//
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#define R_ACPI_IO_PM1_STS 0x00
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#define S_ACPI_IO_PM1_STS 2
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#define B_ACPI_IO_PM1_STS_WAK BIT15
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#define B_ACPI_IO_PM1_STS_PCIEXP_WAKE_STS BIT14
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#define B_ACPI_IO_PM1_STS_PRBTNOR BIT11
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#define B_ACPI_IO_PM1_STS_RTC BIT10
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#define B_ACPI_IO_PM1_STS_PWRBTN BIT8
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#define B_ACPI_IO_PM1_STS_GBL BIT5
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#define B_ACPI_IO_PM1_STS_TMROF BIT0
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#define N_ACPI_IO_PM1_STS_RTC 10
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#define N_ACPI_IO_PM1_STS_PWRBTN 8
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#define N_ACPI_IO_PM1_STS_TMROF 0
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#define R_ACPI_IO_PM1_EN 0x02
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#define S_ACPI_IO_PM1_EN 2
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#define B_ACPI_IO_PM1_EN_PWRBTN BIT8
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#define N_ACPI_IO_PM1_EN_RTC 10
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#define N_ACPI_IO_PM1_EN_PWRBTN 8
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#define N_ACPI_IO_PM1_EN_TMROF 0
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#define R_ACPI_IO_PM1_CNT 0x04
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#define B_ACPI_IO_PM1_CNT_SLP_EN BIT13
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#define B_ACPI_IO_PM1_CNT_SLP_TYP (BIT12 | BIT11 | BIT10)
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#define V_ACPI_IO_PM1_CNT_S0 0
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#define V_ACPI_IO_PM1_CNT_S1 BIT10
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#define V_ACPI_IO_PM1_CNT_S3 (BIT12 | BIT10)
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#define V_ACPI_IO_PM1_CNT_S4 (BIT12 | BIT11)
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#define V_ACPI_IO_PM1_CNT_S5 (BIT12 | BIT11 | BIT10)
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#define B_ACPI_IO_PM1_CNT_SCI_EN BIT0
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#define R_ACPI_IO_PM1_TMR 0x08
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#define B_ACPI_IO_PM1_TMR_VAL 0xFFFFFF
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#define V_ACPI_IO_PM1_TMR_MAX_VAL 0x1000000 ///< The timer is 24 bit overflow
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#define R_ACPI_IO_SMI_EN 0x30
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#define S_ACPI_IO_SMI_EN 4
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#define B_ACPI_IO_SMI_EN_LEGACY_USB2 BIT17
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#define B_ACPI_IO_SMI_EN_TCO BIT13
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#define B_ACPI_IO_SMI_EN_BIOS_RLS BIT7
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#define B_ACPI_IO_SMI_EN_SWSMI_TMR BIT6
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#define B_ACPI_IO_SMI_EN_APMC BIT5
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#define B_ACPI_IO_SMI_EN_LEGACY_USB BIT3
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#define B_ACPI_IO_SMI_EN_BIOS BIT2
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#define B_ACPI_IO_SMI_EN_EOS BIT1
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#define B_ACPI_IO_SMI_EN_GBL_SMI BIT0
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#define N_ACPI_IO_SMI_EN_LEGACY_USB3 31
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#define N_ACPI_IO_SMI_EN_ESPI 28
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#define N_ACPI_IO_SMI_EN_PERIODIC 14
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#define N_ACPI_IO_SMI_EN_TCO 13
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#define N_ACPI_IO_SMI_EN_MCSMI 11
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#define N_ACPI_IO_SMI_EN_SWSMI_TMR 6
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#define N_ACPI_IO_SMI_EN_APMC 5
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#define N_ACPI_IO_SMI_EN_ON_SLP_EN 4
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#define N_ACPI_IO_SMI_EN_LEGACY_USB 3
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#define R_ACPI_IO_SMI_STS 0x34
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#define S_ACPI_IO_SMI_STS 4
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#define B_ACPI_IO_SMI_STS_GPIO_UNLOCK BIT27
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#define B_ACPI_IO_SMI_STS_SMBUS BIT16
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#define B_ACPI_IO_SMI_STS_PERIODIC BIT14
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#define B_ACPI_IO_SMI_STS_TCO BIT13
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#define B_ACPI_IO_SMI_STS_MCSMI BIT11
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#define B_ACPI_IO_SMI_STS_SWSMI_TMR BIT6
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#define B_ACPI_IO_SMI_STS_APM BIT5
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#define B_ACPI_IO_SMI_STS_ON_SLP_EN BIT4
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#define B_ACPI_IO_SMI_STS_BIOS BIT2
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#define N_ACPI_IO_SMI_STS_LEGACY_USB3 31
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#define N_ACPI_IO_SMI_STS_ESPI 28
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#define N_ACPI_IO_SMI_STS_SPI 26
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#define N_ACPI_IO_SMI_STS_MONITOR 21
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#define N_ACPI_IO_SMI_STS_PCI_EXP 20
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#define N_ACPI_IO_SMI_STS_SMBUS 16
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#define N_ACPI_IO_SMI_STS_SERIRQ 15
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#define N_ACPI_IO_SMI_STS_PERIODIC 14
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#define N_ACPI_IO_SMI_STS_TCO 13
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#define N_ACPI_IO_SMI_STS_MCSMI 11
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#define N_ACPI_IO_SMI_STS_GPIO_SMI 10
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#define N_ACPI_IO_SMI_STS_GPE0 9
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#define N_ACPI_IO_SMI_STS_PM1_STS_REG 8
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#define N_ACPI_IO_SMI_STS_SWSMI_TMR 6
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#define N_ACPI_IO_SMI_STS_APM 5
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#define N_ACPI_IO_SMI_STS_ON_SLP_EN 4
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#define N_ACPI_IO_SMI_STS_LEGACY_USB 3
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#define R_ACPI_IO_DEVACT_STS 0x44
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#define B_ACPI_IO_DEVACT_STS_KBC BIT12
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#define B_ACPI_IO_DEVACT_STS_PIRQDH BIT9
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#define B_ACPI_IO_DEVACT_STS_PIRQCG BIT8
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#define B_ACPI_IO_DEVACT_STS_PIRQBF BIT7
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#define B_ACPI_IO_DEVACT_STS_PIRQAE BIT6
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#define R_ACPI_IO_GPE0_STS_127_96 0x6C
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#define S_ACPI_IO_GPE0_STS_127_96 4
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#define B_ACPI_IO_GPE0_STS_127_96_WADT BIT18
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#define B_ACPI_IO_GPE0_STS_127_96_USB_CON_DSX_STS BIT17
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#define B_ACPI_IO_GPE0_STS_127_96_LAN_WAKE BIT16
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#define B_ACPI_IO_GPE0_STS_127_96_PME_B0 BIT13
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#define B_ACPI_IO_GPE0_STS_127_96_PME BIT11
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#define B_ACPI_IO_GPE0_STS_127_96_BATLOW BIT10
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#define B_ACPI_IO_GPE0_STS_127_96_RI BIT8
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#define B_ACPI_IO_GPE0_STS_127_96_SMB_WAK BIT7
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#define B_ACPI_IO_GPE0_STS_127_96_SWGPE BIT2
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#define N_ACPI_IO_GPE0_STS_127_96_PME_B0 13
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#define N_ACPI_IO_GPE0_STS_127_96_PME 11
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#define R_ACPI_IO_GPE0_EN_127_96 0x7C
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#define S_ACPI_IO_GPE0_EN_127_96 4
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#define B_ACPI_IO_GPE0_EN_127_96_WADT BIT18
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#define B_ACPI_IO_GPE0_EN_127_96_LAN_WAKE BIT16
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#define B_ACPI_IO_GPE0_EN_127_96_PME_B0 BIT13
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#define B_ACPI_IO_GPE0_EN_127_96_ME_SCI BIT12
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#define B_ACPI_IO_GPE0_EN_127_96_PME BIT11
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#define B_ACPI_IO_GPE0_EN_127_96_BATLOW BIT10
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#define B_ACPI_IO_GPE0_EN_127_96_RI BIT8
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#define B_ACPI_IO_GPE0_EN_127_96_SWGPE BIT2
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#define N_ACPI_IO_GPE0_EN_127_96_PME_B0 13
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#define N_ACPI_IO_GPE0_EN_127_96_PME 11
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//
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// TCO register I/O map
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//
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#define R_TCO_IO_TCO1_STS 0x04
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#define S_TCO_IO_TCO1_STS 2
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#define B_TCO_IO_TCO1_STS_DMISERR BIT12
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#define B_TCO_IO_TCO1_STS_DMISMI BIT10
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#define B_TCO_IO_TCO1_STS_DMISCI BIT9
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#define B_TCO_IO_TCO1_STS_BIOSWR BIT8
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#define B_TCO_IO_TCO1_STS_NEWCENTURY BIT7
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#define B_TCO_IO_TCO1_STS_TIMEOUT BIT3
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#define B_TCO_IO_TCO1_STS_TCO_INT BIT2
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#define B_TCO_IO_TCO1_STS_SW_TCO_SMI BIT1
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#define N_TCO_IO_TCO1_STS_DMISMI 10
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#define N_TCO_IO_TCO1_STS_BIOSWR 8
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#define N_TCO_IO_TCO1_STS_NEWCENTURY 7
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#define N_TCO_IO_TCO1_STS_TIMEOUT 3
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#define N_TCO_IO_TCO1_STS_SW_TCO_SMI 1
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#define N_TCO_IO_TCO1_STS_NMI2SMI 0
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#define R_TCO_IO_TCO2_STS 0x06
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#define S_TCO_IO_TCO2_STS 2
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#define B_TCO_IO_TCO2_STS_SECOND_TO BIT1
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#define B_TCO_IO_TCO2_STS_INTRD_DET BIT0
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#define N_TCO_IO_TCO2_STS_INTRD_DET 0
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#define R_TCO_IO_TCO1_CNT 0x08
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#define S_TCO_IO_TCO1_CNT 2
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#define B_TCO_IO_TCO1_CNT_LOCK BIT12
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#define N_TCO_IO_TCO1_CNT_NMI2SMI_EN 9
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#define R_TCO_IO_TCO2_CNT 0x0A
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#define S_TCO_IO_TCO2_CNT 2
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#define N_TCO_IO_TCO2_CNT_INTRD_SEL 2
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//
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// PWRM Registers
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//
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#define R_PMC_PWRM_GEN_PMCON_A 0x1020 ///< in CNL located in PWRM
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#define B_PMC_PWRM_GEN_PMCON_A_GBL_RST_STS BIT24
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#define B_PMC_PWRM_GEN_PMCON_A_DISB BIT23
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#define B_PMC_PWRM_GEN_PMCON_A_ALLOW_L1LOW_C0 BIT19
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#define B_PMC_PWRM_GEN_PMCON_A_MS4V BIT18
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#define B_PMC_PWRM_GEN_PMCON_A_SUS_PWR_FLR BIT16
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#define B_PMC_PWRM_GEN_PMCON_A_PWR_FLR BIT14
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#define B_PMC_PWRM_GEN_PMCON_A_HOST_RST_STS BIT9
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#define B_PMC_PWRM_GEN_PMCON_A_ESPI_SMI_LOCK BIT8
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#define B_PMC_PWRM_GEN_PMCON_A_AFTERG3_EN BIT0
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#define B_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL 0xC0
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#define V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_64MS 0xC0
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#define V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_32MS 0x80
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#define V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_16MS 0x40
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#define V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_1_5MS 0x00
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#define B_PMC_PWRM_GEN_PMCON_A_PER_SMI_SEL 0x6
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#define V_PMC_PWRM_GEN_PMCON_A_PER_SMI_64S 0x0000
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#define V_PMC_PWRM_GEN_PMCON_A_PER_SMI_32S 0x0002
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#define V_PMC_PWRM_GEN_PMCON_A_PER_SMI_16S 0x0004
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#define V_PMC_PWRM_GEN_PMCON_A_PER_SMI_8S 0x0006
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#define R_PMC_PWRM_GEN_PMCON_B 0x1024
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#define B_PMC_PWRM_GEN_PMCON_B_SLPSX_STR_POL_LOCK BIT18 ///< Lock down SLP_S3/SLP_S4 Minimum Assertion width
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#define B_PMC_PWRM_GEN_PMCON_B_PWRBTN_LVL BIT9
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#define B_PMC_PWRM_GEN_PMCON_B_SMI_LOCK BIT4
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#define B_PMC_PWRM_GEN_PMCON_B_RTC_PWR_STS BIT2
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#define R_PMC_PWRM_CRID 0x1030 ///< Configured Revision ID
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#define V_PMC_PWRM_CRID_RID_SEL_CRID0 1
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#define B_PMC_PWRM_CRID_CRID_LK BIT31 ///< CRID Lock
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#define R_PMC_PWRM_ETR3 0x1048 ///< in CNL this is PWRM register
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#define B_PMC_PWRM_ETR3_CF9LOCK BIT31 ///< CF9h Lockdown
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#define B_PMC_PWRM_ETR3_CF9GR BIT20 ///< CF9h Global Reset
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#define B_PMC_PWRM_ETR3_CWORWRE BIT18
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#define R_PMC_PWRM_CFG 0x1818 ///< Power Management Configuration
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#define B_PMC_PWRM_CFG_DBG_MODE_LOCK BIT27 ///< Debug Mode Lock
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#define B_PMC_PWRM_CFG_PMCREAD_DISABLE BIT22 ///< Disable Reads to PMC
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#define B_PMC_PWRM_CFG_TIMING_TPCH25 (BIT1 | BIT0) ///< tPCH25 timing
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#define R_PMC_PWRM_DSX_CFG 0x1834 ///< Deep SX Configuration
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#define B_PMC_PWRM_DSX_CFG_LAN_WAKE_EN BIT0 ///< LAN_WAKE Pin DeepSx Enable
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#define R_PMC_PWRM_GPIO_CFG 0x1920
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#define B_PMC_PWRM_GPIO_CFG_GPE0_DW2 (BIT11 | BIT10 | BIT9 | BIT8)
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#define N_PMC_PWRM_GPIO_CFG_GPE0_DW2 8
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#define B_PMC_PWRM_GPIO_CFG_GPE0_DW1 (BIT7 | BIT6 | BIT5 | BIT4)
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#define N_PMC_PWRM_GPIO_CFG_GPE0_DW1 4
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#define B_PMC_PWRM_GPIO_CFG_GPE0_DW0 (BIT3 | BIT2 | BIT1 | BIT0)
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#define N_PMC_PWRM_GPIO_CFG_GPE0_DW0 0
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#define R_PMC_PWRM_HPR_CAUSE0 0x192C ///< Host partition reset causes
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#define B_PMC_PWRM_HPR_CAUSE0_GBL_TO_HOST BIT15 ///< Global reset converted to Host reset
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#define R_PMC_PWRM_ST_PG_FDIS_PMC_1 0x1E20 ///< Static PG Related Function Disable Register 1
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#define B_PMC_PWRM_ST_PG_FDIS_PMC_1_ST_FDIS_LK BIT31 ///< Static Function Disable Lock (ST_FDIS_LK)
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#define R_PMC_PWRM_FUSE_DIS_RD_2 0x1E44 ///< Fuse Disable Read 2 Register
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#define B_PMC_PWRM_FUSE_DIS_RD_2_GBE_FUSE_SS_DIS BIT0 ///< GBE Fuse or Soft Strap Disable
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#endif
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