/** @file
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Register names for PCH PCI-E root port devices
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Conventions:
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- Register definition format:
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Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
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- Prefix:
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Definitions beginning with "R_" are registers
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Definitions beginning with "B_" are bits within registers
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Definitions beginning with "V_" are meaningful values within the bits
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Definitions beginning with "S_" are register size
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Definitions beginning with "N_" are the bit position
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- [GenerationName]:
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Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
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Register name without GenerationName applies to all generations.
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- [ComponentName]:
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This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
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Register name without ComponentName applies to all components.
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Register that is specific to -LP denoted by "_PCH_LP_" in component name.
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- SubsystemName:
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This field indicates the subsystem name of the component that the register belongs to
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(e.g. PCIE, USB, SATA, GPIO, PMC etc.).
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- RegisterSpace:
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MEM - MMIO space register of subsystem.
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IO - IO space register of subsystem.
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PCR - Private configuration register of subsystem.
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CFG - PCI configuration space register of subsystem.
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- RegisterName:
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Full register name.
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Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _PCH_REGS_PCIE_H_
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#define _PCH_REGS_PCIE_H_
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#define R_PCH_PCIE_CFG_CLIST 0x40
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#define R_PCH_PCIE_CFG_LCAP (R_PCH_PCIE_CFG_CLIST + R_PCIE_LCAP_OFFSET)
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#define N_PCH_PCIE_CFG_LCAP_PN 24
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#define R_PCH_PCIE_CFG_LCTL (R_PCH_PCIE_CFG_CLIST + R_PCIE_LCTL_OFFSET)
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#define R_PCH_PCIE_CFG_LSTS (R_PCH_PCIE_CFG_CLIST + R_PCIE_LSTS_OFFSET)
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#define R_PCH_PCIE_CFG_SLCAP (R_PCH_PCIE_CFG_CLIST + R_PCIE_SLCAP_OFFSET)
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#define R_PCH_PCIE_CFG_SLSTS (R_PCH_PCIE_CFG_CLIST + R_PCIE_SLSTS_OFFSET)
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#define R_PCH_PCIE_CFG_MPC2 0xD4
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#define B_PCH_PCIE_CFG_MPC2_EOIFD BIT1
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#define R_PCH_PCIE_CFG_MPC 0xD8
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#define S_PCH_PCIE_CFG_MPC 4
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#define B_PCH_PCIE_CFG_MPC_PMCE BIT31
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#define B_PCH_PCIE_CFG_MPC_HPME BIT1
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#define N_PCH_PCIE_CFG_MPC_HPME 1
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#define R_PCH_PCIE_CFG_SMSCS 0xDC
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#define S_PCH_PCIE_CFG_SMSCS 4
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#define B_PCH_PCIE_CFG_SMSCS_PMCS BIT31
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#define N_PCH_PCIE_CFG_SMSCS_LERSMIS 5
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#define N_PCH_PCIE_CFG_SMSCS_HPLAS 4
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#define N_PCH_PCIE_CFG_SMSCS_HPPDM 1
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//CES.RE, CES.BT, CES.BD
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#define R_PCH_PCIE_CFG_EX_SPEECH 0xA30 ///< Secondary PCI Express Extended Capability Header
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#define R_PCH_PCIE_CFG_EX_LCTL3 (R_PCH_PCIE_CFG_EX_SPEECH + R_PCIE_EX_LCTL3_OFFSET)
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#define R_PCH_PCIE_CFG_LTROVR 0x400
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#define B_PCH_PCIE_CFG_LTROVR_LTRNSROVR BIT31 ///< LTR Non-Snoop Requirement Bit Override
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#define B_PCH_PCIE_CFG_LTROVR_LTRSROVR BIT15 ///< LTR Snoop Requirement Bit Override
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#define R_PCH_PCIE_CFG_LTROVR2 0x404
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#define B_PCH_PCIE_CFG_LTROVR2_FORCE_OVERRIDE BIT3 ///< LTR Force Override Enable
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#define B_PCH_PCIE_CFG_LTROVR2_LOCK BIT2 ///< LTR Override Lock
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#define B_PCH_PCIE_CFG_LTROVR2_LTRNSOVREN BIT1 ///< LTR Non-Snoop Override Enable
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#define B_PCH_PCIE_CFG_LTROVR2_LTRSOVREN BIT0 ///< LTR Snoop Override Enable
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#define R_PCH_PCIE_CFG_PCIEPMECTL 0x420
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#define B_PCH_PCIE_CFG_PCIEPMECTL_DLSULPPGE BIT30
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#define B_PCH_PCIE_CFG_PCIEPMECTL_L1LE BIT17
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#define B_PCH_PCIE_CFG_PCIEPMECTL_L1FSOE BIT0
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#define R_PCH_PCIE_CFG_EQCFG1 0x450
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#define S_PCH_PCIE_CFG_EQCFG1 4
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#define N_PCH_PCIE_CFG_EQCFG1_LERSMIE 21
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//
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// PCIE PCRs (PID:SPA SPB SPC SPD SPE SPF)
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//
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#define R_SPX_PCR_PCD 0 ///< Port configuration and disable
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#define B_SPX_PCR_PCD_RP1FN (BIT2 | BIT1 | BIT0) ///< Port 1 Function Number
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#define S_SPX_PCR_PCD_RP_FIELD 4 ///< 4 bits for each RP FN
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#endif
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