/** @file
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Register names for Flash registers
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Conventions:
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- Register definition format:
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Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
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- Prefix:
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Definitions beginning with "R_" are registers
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Definitions beginning with "B_" are bits within registers
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Definitions beginning with "V_" are meaningful values within the bits
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Definitions beginning with "S_" are register size
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Definitions beginning with "N_" are the bit position
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- [GenerationName]:
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Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
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Register name without GenerationName applies to all generations.
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- [ComponentName]:
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This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
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Register name without ComponentName applies to all components.
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Register that is specific to -LP denoted by "_PCH_LP_" in component name.
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- SubsystemName:
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This field indicates the subsystem name of the component that the register belongs to
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(e.g. PCIE, USB, SATA, GPIO, PMC etc.).
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- RegisterSpace:
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MEM - MMIO space register of subsystem.
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IO - IO space register of subsystem.
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PCR - Private configuration register of subsystem.
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CFG - PCI configuration space register of subsystem.
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- RegisterName:
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Full register name.
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Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _FLASH_REGS_H_
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#define _FLASH_REGS_H_
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//
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// Flash Descriptor Base Address Region (FDBAR) from Flash Region 0
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//
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#define R_FLASH_FDBAR_FLASH_MAP0 0x04
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#define B_FLASH_FDBAR_NC 0x00000300 ///< Number Of Components
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#define N_FLASH_FDBAR_NC 8 ///< Number Of Components
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#define R_FLASH_FDBAR_FLASH_MAP1 0x08
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#define B_FLASH_FDBAR_FPSBA 0x00FF0000 ///< PCH Strap Base Address, [23:16] represents [11:4]
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#define N_FLASH_FDBAR_FPSBA 16 ///< PCH Strap base Address bit position
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#define N_FLASH_FDBAR_FPSBA_REPR 4 ///< PCH Strap base Address bit represents position
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#define B_FLASH_FDBAR_PCHSL 0xFF000000 ///< PCH Strap Length, [31:24] represents number of Dwords
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#define N_FLASH_FDBAR_PCHSL 24 ///< PCH Strap Length bit position
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#define R_FLASH_FDBAR_FLASH_MAP2 0x0C
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#define B_FLASH_FDBAR_FCPUSBA 0x00000FFC ///< CPU Strap Base Address [11:2]
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#define N_FLASH_FDBAR_FCPUSBA 2 ///< CPU Strap Base Address bit position
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#define B_FLASH_FDBAR_CPUSL 0x00FF0000 ///< CPU Strap Length, [23:16] represents number of Dwords
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#define N_FLASH_FDBAR_CPUSL 16 ///< CPU Strap Length bit position
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//
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// Flash Component Base Address (FCBA) from Flash Region 0
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//
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#define R_FLASH_FCBA_FLCOMP 0x00 ///< Flash Components Register
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#define B_FLASH_FLCOMP_COMP1_MASK 0xF0 ///< Flash Component 1 Size MASK
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#define N_FLASH_FLCOMP_COMP1 4 ///< Flash Component 1 Size bit position
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#define B_FLASH_FLCOMP_COMP0_MASK 0x0F ///< Flash Component 0 Size MASK
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#define V_FLASH_FLCOMP_COMP_512KB 0x80000
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//
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// Descriptor Upper Map Section from Flash Region 0
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//
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#define R_FLASH_UMAP1 0xEFC ///< Flash Upper Map 1
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#define B_FLASH_UMAP1_MDTBA 0xFF000000 ///< MIP Descriptor Table Base Address
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#define N_FLASH_UMAP1_MDTBA 24 ///< MDTBA bits position
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#define N_FLASH_UMAP1_MDTBA_REPR 4 ///< MDTBA address representation position
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#endif
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