/** @file
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Register names for PCIE standard register
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Conventions:
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- Prefixes:
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Definitions beginning with "R_" are registers
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Definitions beginning with "B_" are bits within registers
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Definitions beginning with "V_" are meaningful values within the bits
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Definitions beginning with "S_" are register sizes
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Definitions beginning with "N_" are the bit position
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Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _PCIE_REGS_H_
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#define _PCIE_REGS_H_
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#include <IndustryStandard/Pci30.h>
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//
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// PCI type 0 Header
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//
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#define R_PCI_BCC_OFFSET 0x0B
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//
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// PCI type 1 Header
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//
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#define R_PCI_BRIDGE_BNUM 0x18 ///< Bus Number Register
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#define B_PCI_BRIDGE_BNUM_SBBN 0x00FF0000 ///< Subordinate Bus Number
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#define B_PCI_BRIDGE_BNUM_SCBN 0x0000FF00 ///< Secondary Bus Number
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//
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// PCI Express Capability List Register (CAPID:10h)
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//
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#define R_PCIE_XCAP_OFFSET 0x02 ///< PCI Express Capabilities Register (Offset 02h)
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#define B_PCIE_XCAP_DT (BIT7 | BIT6 | BIT5 | BIT4) ///< Device/Port Type
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#define N_PCIE_XCAP_DT 4
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#define R_PCIE_DCAP_OFFSET 0x04 ///< Device Capabilities Register (Offset 04h)
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#define B_PCIE_DCAP_RBER BIT15 ///< Role-Based Error Reporting
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#define B_PCIE_DCAP_E1AL (BIT11 | BIT10 | BIT9) ///< Endpoint L1 Acceptable Latency
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#define N_PCIE_DCAP_E1AL 9
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#define B_PCIE_DCAP_E0AL (BIT8 | BIT7 | BIT6) ///< Endpoint L0s Acceptable Latency
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#define N_PCIE_DCAP_E0AL 6
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#define B_PCIE_DCAP_MPS (BIT2 | BIT1 | BIT0) ///< Max_Payload_Size Supported
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#define R_PCIE_DCTL_OFFSET 0x08 ///< Device Control Register (Offset 08h)
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#define B_PCIE_DCTL_MPS (BIT7 | BIT6 | BIT5) ///< Max_Payload_Size
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#define N_PCIE_DCTL_MPS 5
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#define R_PCIE_LCAP_OFFSET 0x0C ///< Link Capabilities Register (Offset 0Ch)
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#define B_PCIE_LCAP_CPM BIT18 ///< Clock Power Management
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#define B_PCIE_LCAP_EL1 (BIT17 | BIT16 | BIT15) ///< L1 Exit Latency
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#define N_PCIE_LCAP_EL1 15
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#define B_PCIE_LCAP_EL0 (BIT14 | BIT13 | BIT12) ///< L0s Exit Latency
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#define N_PCIE_LCAP_EL0 12
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#define B_PCIE_LCAP_APMS_L0S BIT10
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#define B_PCIE_LCAP_APMS_L1 BIT11
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#define B_PCIE_LCAP_MLS (BIT3 | BIT2 | BIT1 | BIT0) ///< Max Link Speed
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#define V_PCIE_LCAP_MLS_GEN3 3
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#define V_PCIE_LCAP_MLS_GEN4 4
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#define R_PCIE_LCTL_OFFSET 0x10 ///< Link Control Register (Offset 10h)
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#define B_PCIE_LCTL_ECPM BIT8 ///< Enable Clock Power Management
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#define B_PCIE_LCTL_CCC BIT6 ///< Common Clock Configuration
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#define B_PCIE_LCTL_RL BIT5 ///< Retrain Link
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#define B_PCIE_LCTL_ASPM (BIT1 | BIT0) ///< Active State Power Management (ASPM) Control
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#define V_PCIE_LCTL_ASPM_L0S 1
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#define V_PCIE_LCTL_ASPM_L1 2
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#define V_PCIE_LCTL_ASPM_L0S_L1 3
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#define R_PCIE_LSTS_OFFSET 0x12 ///< Link Status Register (Offset 12h)
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#define B_PCIE_LSTS_LA BIT13 ///< Data Link Layer Link Active
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#define B_PCIE_LSTS_SCC BIT12 ///< Slot Clock Configuration
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#define B_PCIE_LSTS_LT BIT11 ///< Link Training
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#define B_PCIE_LSTS_NLW 0x03F0 ///< Negotiated Link Width
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#define N_PCIE_LSTS_NLW 4
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#define B_PCIE_LSTS_CLS 0x000F ///< Current Link Speed
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#define R_PCIE_SLCAP_OFFSET 0x14 ///< Slot Capabilities Register (Offset 14h)
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#define B_PCIE_SLCAP_HPC BIT6 ///< Hot-Plug Capable
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#define R_PCIE_SLSTS_OFFSET 0x1A ///< Slot Status Register (Offset 1Ah)
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#define B_PCIE_SLSTS_PDS BIT6 ///< Presence Detect State
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#define R_PCIE_DCAP2_OFFSET 0x24 ///< Device Capabilities 2 Register (Offset 24h)
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#define B_PCIE_DCAP2_LTRMS BIT11 ///< LTR Mechanism Supported
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#define R_PCIE_DCTL2_OFFSET 0x28 ///< Device Control 2 Register (Offset 28h)
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#define B_PCIE_DCTL2_LTREN BIT10 ///< LTR Mechanism Enable
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#define B_PCIE_LCTL2_TLS (BIT3 | BIT2 | BIT1 | BIT0) ///< Target Link Speed
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//
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// Latency Tolerance Reporting Extended Capability Registers (CAPID:0018h)
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//
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#define R_PCIE_LTRECH_CID 0x0018
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#define R_PCIE_LTRECH_MSLR_OFFSET 0x04
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#define N_PCIE_LTRECH_MSLR_VALUE 0
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#define N_PCIE_LTRECH_MSLR_SCALE 10
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#define R_PCIE_LTRECH_MNSLR_OFFSET 0x06
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#define N_PCIE_LTRECH_MNSLR_VALUE 0
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#define N_PCIE_LTRECH_MNSLR_SCALE 10
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//
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// Secondary PCI Express Extended Capability Header (CAPID:0019h)
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//
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#define R_PCIE_EX_LCTL3_OFFSET 0x04 ///< Link Control 3 Register
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#define B_PCIE_EX_LCTL3_PE BIT0 ///< Perform Equalization
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//
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// L1 Sub-States Extended Capability Register (CAPID:001Eh)
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//
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#define V_PCIE_EX_L1S_CID 0x001E ///< Capability ID
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#define R_PCIE_EX_L1SCAP_OFFSET 0x04 ///< L1 Sub-States Capabilities
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#define B_PCIE_EX_L1SCAP_PTV 0x00F80000 //< Port Tpower_on value
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#define N_PCIE_EX_L1SCAP_PTV 19
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#define B_PCIE_EX_L1SCAP_PTPOS 0x00030000 //< Port Tpower_on scale
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#define N_PCIE_EX_L1SCAP_PTPOS 16
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#define B_PCIE_EX_L1SCAP_CMRT 0x0000FF00 //< Common Mode Restore time
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#define N_PCIE_EX_L1SCAP_CMRT 8
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#define B_PCIE_EX_L1SCAP_L1PSS BIT4 ///< L1 PM substates supported
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#define B_PCIE_EX_L1SCAP_AL1SS BIT3 ///< ASPM L1.1 supported
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#define B_PCIE_EX_L1SCAP_AL12S BIT2 ///< ASPM L1.2 supported
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#define B_PCIE_EX_L1SCAP_PPL11S BIT1 ///< PCI-PM L1.1 supported
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#define B_PCIE_EX_L1SCAP_PPL12S BIT0 ///< PCI-PM L1.2 supported
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#define R_PCIE_EX_L1SCTL1_OFFSET 0x08 ///< L1 Sub-States Control 1
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#define B_PCIE_EX_L1SCTL1_L1SSEIE BIT4
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#define N_PCIE_EX_L1SCTL1_L12LTRTLSV 29
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#define N_PCIE_EX_L1SCTL1_L12LTRTLV 16
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#define R_PCIE_EX_L1SCTL2_OFFSET 0x0C ///< L1 Sub-States Control 2
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#define N_PCIE_EX_L1SCTL2_POWT 3
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//
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// PTM Extended Capability Register (CAPID:001Fh)
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//
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#define V_PCIE_EX_PTM_CID 0x001F ///< Capability ID
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#define R_PCIE_EX_PTMCAP_OFFSET 0x04 ///< PTM Capabilities
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#define R_PCIE_EX_PTMCTL_OFFSET 0x08 ///< PTM Control Register
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//
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// Base Address Offset
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//
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#define B_PCI_BAR_MEMORY_TYPE_MASK (BIT1 | BIT2)
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#define B_PCI_BAR_MEMORY_TYPE_64 BIT2
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//
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// PCI Express Extended Capability Header
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//
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#define R_PCIE_CFG_EXCAP_OFFSET 0x100
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#endif
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