/** @file
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Header file for PmcLib.
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Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _PMC_LIB_H_
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#define _PMC_LIB_H_
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#pragma pack(1)
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typedef enum {
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PmcTPch25_10us = 0,
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PmcTPch25_100us,
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PmcTPch25_1ms,
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PmcTPch25_10ms,
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} PMC_TPCH25_TIMING;
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typedef enum {
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PmcNotASleepState,
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PmcInS0State,
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PmcS1SleepState,
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PmcS2SleepState,
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PmcS3SleepState,
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PmcS4SleepState,
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PmcS5SleepState,
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PmcUndefinedState,
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} PMC_SLEEP_STATE;
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typedef struct {
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UINT32 Buf0;
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UINT32 Buf1;
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UINT32 Buf2;
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UINT32 Buf3;
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} PMC_IPC_COMMAND_BUFFER;
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//
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// Structure to Check different attributes for CrashLog supported by PMC.
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//
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typedef union {
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struct {
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UINT32 Avail : 1; ///< CrashLog feature availability bit
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UINT32 Dis : 1; ///< CrasLog Disable bit
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UINT32 Rsvd : 2; ///< Reserved
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UINT32 Size : 12; ///< CrasLog data size. (If it is zero, use default size 0xC00)
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UINT32 BaseOffset : 16; ///< Start offset of CrashLog in PMC SSRAM
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} Bits;
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struct {
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UINT32 Avail : 1; ///< CrashLog feature availability bit
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UINT32 Dis : 1; ///< CrasLog Disable bit
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UINT32 Mech : 2; ///< CrashLog mechanism
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UINT32 ManuTri : 1; ///< Manul trigger command.
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UINT32 Clr : 1; ///< Clear Command
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UINT32 AllReset : 1; ///< Trigger on all reset command
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UINT32 ReArm : 1; ///< Re-arm command
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UINT32 Rsvd : 20; ///< Pch Specific reserved
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UINT32 CrashLogReq: 1; ///< Crash log requestor flow
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UINT32 TriArmedSts: 1; ///< Trigger armed status, re-arm indication bit.
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UINT32 TriAllReset: 1; ///< Trigger on all resets status
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UINT32 CrashDisSts: 1; ///< Crash log disabled status
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UINT32 PchRsvd : 16; ///< Pch Specific reserved
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UINT32 DesTableOffset: 16; ///< Descriptor Table offset
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} Bits64;
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UINT32 Uint32;
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UINT64 Uint64;
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} PMC_IPC_DISCOVERY_BUF;
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typedef union {
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struct {
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UINT32 Offset : 16;
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UINT32 Size : 16;
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} Info;
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UINT32 Uint32;
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} PMC_CRASHLOG_RECORDS;
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typedef struct PmcCrashLogLink {
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PMC_CRASHLOG_RECORDS Record;
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UINT64 AllocateAddress;
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struct PmcCrashLogLink *Next;
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} PMC_CRASHLOG_LINK;
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#pragma pack()
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/**
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Get PCH ACPI base address.
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@retval Address Address of PWRM base address.
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**/
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UINT16
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PmcGetAcpiBase (
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VOID
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);
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/**
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Get PCH PWRM base address.
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@retval Address Address of PWRM base address.
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**/
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UINT32
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PmcGetPwrmBase (
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VOID
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);
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/**
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This function sets tPCH25 timing
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@param[in] TimingValue tPCH25 timing value (10us, 100us, 1ms, 10ms)
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**/
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VOID
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PmcSetTPch25Timing (
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IN PMC_TPCH25_TIMING TimingValue
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);
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/**
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This function checks if RTC Power Failure occurred by
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reading RTC_PWR_FLR bit
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@retval RTC Power Failure state: TRUE - Battery is always present.
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FALSE - CMOS is cleared.
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**/
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BOOLEAN
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PmcIsRtcBatteryGood (
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VOID
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);
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/**
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This function checks if Power Failure occurred by
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reading PWR_FLR bit
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@retval Power Failure state
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**/
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BOOLEAN
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PmcIsPowerFailureDetected (
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VOID
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);
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/**
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This function checks if Power Failure occurred by
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reading SUS_PWR_FLR bit
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@retval SUS Power Failure state
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**/
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BOOLEAN
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PmcIsSusPowerFailureDetected (
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VOID
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);
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/**
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This function clears Power Failure status (PWR_FLR)
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**/
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VOID
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PmcClearPowerFailureStatus (
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VOID
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);
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/**
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This function clears Global Reset status (GBL_RST_STS)
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**/
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VOID
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PmcClearGlobalResetStatus (
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VOID
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);
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/**
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This function clears Host Reset status (HOST_RST_STS)
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**/
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VOID
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PmcClearHostResetStatus (
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VOID
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);
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/**
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This function clears SUS Power Failure status (SUS_PWR_FLR)
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**/
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VOID
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PmcClearSusPowerFailureStatus (
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VOID
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);
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/**
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This function sets state to which platform will get after power is reapplied
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@param[in] PowerStateAfterG3 0: S0 state (boot)
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1: S5/S4 State
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**/
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VOID
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PmcSetPlatformStateAfterPowerFailure (
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IN UINT8 PowerStateAfterG3
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);
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/**
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This function enables Power Button SMI
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**/
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VOID
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PmcEnablePowerButtonSmi (
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VOID
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);
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/**
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This function disables Power Button SMI
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**/
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VOID
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PmcDisablePowerButtonSmi (
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VOID
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);
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/**
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This function reads PM Timer Count driven by 3.579545 MHz clock
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@retval PM Timer Count
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**/
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UINT32
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PmcGetTimerCount (
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VOID
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);
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/**
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Get Sleep Type that platform has waken from
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@retval SleepType Sleep Type
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**/
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PMC_SLEEP_STATE
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PmcGetSleepTypeAfterWake (
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VOID
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);
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/**
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Clear PMC Wake Status
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**/
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VOID
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PmcClearWakeStatus (
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VOID
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);
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/**
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Configure sleep state
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@param[in] SleepState S0/S1/S3/S4/S5, refer to PMC_SLEEP_STATE
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**/
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VOID
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PmcSetSleepState (
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PMC_SLEEP_STATE SleepState
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);
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/**
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Check if platform boots after shutdown caused by power button override event
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@retval TRUE Power Button Override occurred in last system boot
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@retval FALSE Power Button Override didn't occur
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**/
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BOOLEAN
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PmcIsPowerButtonOverrideDetected (
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VOID
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);
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/**
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This function will set the DISB - DRAM Initialization Scratchpad Bit.
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**/
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VOID
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PmcSetDramInitScratchpad (
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VOID
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);
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/**
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Check global SMI enable is set
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@retval TRUE Global SMI enable is set
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FALSE Global SMI enable is not set
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**/
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BOOLEAN
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PmcIsGblSmiEn (
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VOID
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);
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/**
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This function checks if SMI Lock is set
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@retval SMI Lock state
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**/
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BOOLEAN
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PmcIsSmiLockSet (
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VOID
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);
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/**
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This function checks if Debug Mode is locked
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@retval Debug Mode Lock state
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**/
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BOOLEAN
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PmcIsDebugModeLocked (
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VOID
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);
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/**
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Check TCO second timeout status.
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@retval TRUE TCO reboot happened.
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@retval FALSE TCO reboot didn't happen.
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**/
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BOOLEAN
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TcoSecondToHappened (
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VOID
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);
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/**
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This function clears the Second TO status bit
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**/
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VOID
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TcoClearSecondToStatus (
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VOID
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);
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/**
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Check TCO SMI ENABLE is locked
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@retval TRUE TCO SMI ENABLE is locked
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FALSE TCO SMI ENABLE is not locked
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**/
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BOOLEAN
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TcoIsSmiLock (
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VOID
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);
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/**
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Check if user wants to turn off in PEI phase
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**/
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VOID
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CheckPowerOffNow(
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VOID
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);
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/**
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Clear any SMI status or wake status left from boot.
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**/
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VOID
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ClearSmiAndWake (
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VOID
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);
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/**
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Function to check if Dirty Warm Reset occurs
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(Global Reset has been converted to Host Reset)
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@reval TRUE DWR occurs
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@reval FALSE Normal boot flow
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**/
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BOOLEAN
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PmcIsDwrBootMode (
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VOID
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);
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#endif // _PMC_LIB_H_
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