/** @file
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The GUID definition for CpuPcieHob
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Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _CPU_PCIE_HOB_H_
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#define _CPU_PCIE_HOB_H_
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#include <Base.h>
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#include <CpuPcieInfo.h>
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#include <CpuPcieConfig.h>
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extern EFI_GUID gCpuPcieHobGuid;
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#pragma pack (push,1)
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/**
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The CPU_PCIE_HOB block describes the expected configuration of the CpuPcie controllers
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**/
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typedef struct {
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///
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/// These members describe the configuration of each CPU PCIe root port.
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///
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EFI_HOB_GUID_TYPE EfiHobGuidType; ///< Offset 0 - 23: GUID Hob type structure for gCpuPcieHobGuid
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CPU_PCIE_ROOT_PORT_CONFIG RootPort[CPU_PCIE_MAX_ROOT_PORTS];
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UINT8 L1SubStates[CPU_PCIE_MAX_ROOT_PORTS]; ///< The L1 Substates configuration of the root port
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UINT32 DekelFwVersionMinor; ///< Dekel Firmware Minor Version
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UINT32 DekelFwVersionMajor; ///< Dekel Firmware Major Version
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BOOLEAN InitPcieAspmAfterOprom; ///< 1=initialize PCIe ASPM after Oprom; 0=before (This will be set basing on policy)
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UINT32 RpEnabledMask; ///< Rootport enabled mask based on DEVEN register
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UINT32 RpEnMaskFromDevEn; ///< Rootport enabled mask based on Device Id
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UINT8 DisableClkReqMsg[CPU_PCIE_MAX_ROOT_PORTS]; ///< 1=ClkReqMsg disabled, 0=ClkReqMsg enabled
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UINT8 SlotSelection; ///< 1=M2 slot, 0=CEMx4 slot
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BOOLEAN ComplianceTest; ///< Compliance Test based on policy
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} CPU_PCIE_HOB;
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#pragma pack (pop)
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#endif
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