/** @file
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CPU Power Management VR Config Block.
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Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _CPU_POWER_MGMT_VR_CONFIG_H_
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#define _CPU_POWER_MGMT_VR_CONFIG_H_
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#define CPU_POWER_MGMT_VR_CONFIG_REVISION 7
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extern EFI_GUID gCpuPowerMgmtVrConfigGuid;
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#pragma pack (push,1)
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///
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/// Defines the maximum number of VR domains supported.
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/// @warning: Changing this define would cause DWORD alignment issues in policy structures.
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///
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#define MAX_NUM_VRS 5
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/**
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CPU Power Management VR Configuration Structure.
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<b>Revision 1</b>:
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- Initial version.
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<b>Revision 2</b>:
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- Updated Acoustic Noise Mitigation.
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<b>Revision 3</b>:
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- Deprecate PsysOffset and added PsysOffset1 for Psys Offset Correction
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<b>Revision 4</b>:
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- Deprecate TdcTimeWindow and added TdcTimeWindow1 for TDC Time
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Added Irms support.
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<b>Revision 5</b>:
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- Add RfiMitigation.
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<b>Revision 6</b>:
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- Added an option to Enable/Disable FIVR Spread Spectrum
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<b>Revision 7</b>:
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- Add Dynamic Periodicity Alteration (DPA) tuning feature
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**/
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typedef struct {
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CONFIG_BLOCK_HEADER Header; ///< Config Block Header
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UINT32 AcousticNoiseMitigation : 1; ///< Enable or Disable Acoustic Noise Mitigation feature. <b>0: Disabled</b>; 1: Enabled
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/**
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VR specific mailbox commands.
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<b>00b - no VR specific command sent.</b>
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01b - A VR mailbox command specifically for the MPS IMPV8 VR will be sent.
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10b - VR specific command sent for PS4 exit issue.
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11b - Reserved.
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**/
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UINT32 SendVrMbxCmd : 2;
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UINT32 EnableMinVoltageOverride : 1; ///< Enable or disable Minimum Voltage override for minimum voltage runtime and minimum voltage C8. <b>0: Disabled</b> 1: Enabled.
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UINT32 RfiMitigation : 1; ///< Enable or Disable RFI Mitigation. <b>0: Disable - DCM is the IO_N default</b>; 1: Enable - Enable IO_N DCM/CCM switching as RFI mitigation.
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UINT32 RsvdBits : 27; ///< Reserved for future use.
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UINT8 PsysSlope; ///< PCODE MMIO Mailbox: Platform Psys slope correction. <b>0: Auto</b> Specified in 1/100 increment values. Range is 0-200. 125 = 1.25.
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UINT8 PsysOffset; ///< PCODE MMIO Mailbox: Platform Psys offset correction. <b>0: Auto</b> Units 1/4, Range 0-255. Value of 100 = 100/4 = 25 offset. Deprecated
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UINT8 FivrSpreadSpectrum; ///< Set the Spread Spectrum Range. <b>1.5%</b>, Range: 0.5%, 1%, 1.5%, 2%, 3%, 4%, 5%, 6%. Each Range is translated to internally encoded values. 0.5% = 0, 1% = 3, 1.5% = 8, 2% = 18, 3% = 28, 4% = 34, 5% = 39, 6% = 44.
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UINT8 RsvdBytes0;
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/**
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PCODE MMIO Mailbox: Set the desired RFI frequency, in increments of 100KHz.
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<b>0: Auto</b>
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Range varies based on XTAL clock:
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- 0-1918 (Up to 191.8HMz) for 24MHz clock.
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- 0-1535 (Up to 153.5MHz) for 19MHz clock.
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**/
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UINT16 FivrRfiFrequency;
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UINT8 RsvdBytes1[2];
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/** @name VR Settings
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The VR related settings are sorted in an array where each index maps to the VR domain as defined below:
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- 0 = System Agent VR
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- 1 = IA Core VR
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- 2 = Ring Vr
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- 3 = GT VR
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- 4 = FIVR VR
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The VR settings for a given domain must be populated in the appropriate index.
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**/
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///@{
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UINT16 TdcCurrentLimit[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: Thermal Design Current current limit. Specified in 1/8A units. Range is 0-4095. 1000 = 125A. <b>0: 0 Amps</b>
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UINT16 AcLoadline[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: AcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is 0-6249. <b>Intel Recommended Defaults vary by domain and SKU.</b>
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UINT16 DcLoadline[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: DcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is 0-6249.<b>Intel Recommended Defaults vary by domain and SKU.</b>
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UINT16 Psi1Threshold[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: Power State 1 current cuttof in 1/4 Amp increments. Range is 0-128A.
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UINT16 Psi2Threshold[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: Power State 2 current cuttof in 1/4 Amp increments. Range is 0-128A.
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UINT16 Psi3Threshold[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: Power State 3 current cuttof in 1/4 Amp increments. Range is 0-128A.
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INT16 ImonOffset[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: Imon offset correction. Value is a 2's complement signed integer. Units 1/1000, Range 0-63999. For an offset = 12.580, use 12580. <b>0: Auto</b>
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UINT16 IccMax[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: VR Icc Max limit. 0-255A in 1/4 A units. 400 = 100A. <b>Default: 0 - Auto, no override</b>
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UINT16 VrVoltageLimit[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: VR Voltage Limit. Range is 0-7999mV.
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UINT16 ImonSlope[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values. Range is 0-200. 125 = 1.25. <b>0: Auto</b>
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UINT8 Psi3Enable[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: Power State 3 enable/disable; 0: Disable; <b>1: Enable</b>.
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UINT8 Psi4Enable[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: Power State 4 enable/disable; 0: Disable; <b>1: Enable</b>.
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UINT8 VrConfigEnable[MAX_NUM_VRS]; ///< Enable/Disable BIOS configuration of VR; 0: Disable; <b>1: Enable.</b>
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UINT8 TdcEnable[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: Thermal Design Current enable/disable; <b>0: Disable; </b>1: Enable
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UINT8 TdcTimeWindow[MAX_NUM_VRS]; ///< @deprecated. PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds. <b>1ms default</b>
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UINT8 TdcLock[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: Thermal Design Current Lock; <b>0: Disable</b>; 1: Enable.
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UINT8 FastPkgCRampDisable[MAX_NUM_VRS]; ///< Disable Fast Slew Rate for Deep Package C States for VR IA,GT,SA,VLCC,FIVR domain based on Acoustic Noise Mitigation feature enabled. <b>0: False</b>; 1: True
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UINT8 SlowSlewRate[MAX_NUM_VRS]; ///< Slew Rate configuration for Deep Package C States for VR VR IA,GT,SA,VLCC,FIVR domain based on Acoustic Noise Mitigation feature enabled. <b>0: Fast/2</b>; 1: Fast/4; 2: Fast/8; 3: Fast/16
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///@}
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UINT16 MinVoltageRuntime; ///< PCODE MMIO Mailbox: Minimum voltage for runtime. Valid if EnableMinVoltageOverride = 1 .Range 0 to 1999mV. <b> 0: 0mV </b>
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UINT16 MinVoltageC8; ///< PCODE MMIO Mailbox: Minimum voltage for C8. Valid if EnableMinVoltageOverride = 1. Range 0 to 1999mV. <b> 0: 0mV </b>
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UINT16 PsysOffset1; ///< PCODE MMIO Mailbox: Platform Psys offset correction. <b>0: Auto</b> Units 1/1000, Range 0-63999. For an offset of 25.348, enter 25348.
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UINT8 RsvdBytes2[2];
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UINT32 TdcTimeWindow1[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds. <b>1ms default</b>
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UINT8 Irms[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: Current root mean square. <b>0: Disable</b>; 1: Enable.
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UINT8 FivrSpectrumEnable; ///< Enable or Disable FIVR Spread Spectrum 0: Disable; <b> 1: Enable.</b>
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UINT8 Rsvd1[2];
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UINT8 PreWake; ///< PCODE MMIO Mailbox: Acoustic Noise Mitigation Range. This can be programmed only if AcousticNoiseMitigation is enabled.<b>Default Value = 0 micro ticks</b> Defines the max pre-wake randomization time in micro ticks. Range is 0-255.
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UINT8 RampUp; ///< PCODE MMIO Mailbox: Acoustic Noise Mitigation Range. This can be programmed only if AcousticNoiseMitigation is enabled.<b>Default Value = 0 micro ticks</b> Defines the max ramp up randomization time in micro ticks. Range is 0-255.
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UINT8 RampDown; ///< PCODE MMIO Mailbox: Acoustic Noise Mitigation Range. This can be programmed only if AcousticNoiseMitigation is enabled.<b>Default Value = 0 micro ticks</b> Defines the max ramp down randomization time in micro ticks. Range is 0-255.
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UINT8 Rsvd2[1];
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} CPU_POWER_MGMT_VR_CONFIG;
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#pragma pack (pop)
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#endif // _CPU_POWER_MGMT_VR_CONFIG_H_
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