/** @file
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USB3 Mod PHY configuration policy
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Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _USB3_HSIO_CONFIG_H_
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#define _USB3_HSIO_CONFIG_H_
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#include <UsbConfig.h>
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#define USB3_HSIO_CONFIG_REVISION 2
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extern EFI_GUID gUsb3HsioConfigGuid;
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#pragma pack (push,1)
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/**
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This structure describes USB3 Port N configuration parameters
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**/
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typedef struct {
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/**
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USB 3.0 TX Output Downscale Amplitude Adjustment (orate01margin)
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HSIO_TX_DWORD8[21:16]
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<b>Default = 00h</b>
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**/
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UINT8 HsioTxDownscaleAmp;
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/**
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USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting (ow2tapgen2deemph3p5)
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HSIO_TX_DWORD5[21:16]
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<b>Default = 29h</b> (approximately -3.5dB De-Emphasis)
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**/
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UINT8 HsioTxDeEmph;
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/**
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Signed Magnatude number added to the CTLE code.(ctle_adapt_offset_cfg_4_0)
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HSIO_RX_DWORD25 [20:16]
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Ex: -1 -- 1_0001. +1: 0_0001
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<b>Default = 0h</b>
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**/
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UINT8 HsioCtrlAdaptOffsetCfg;
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/**
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LFPS filter select for n (filter_sel_n_2_0)
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HSIO_RX_DWORD51 [29:27]
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0h:1.6ns
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1h:2.4ns
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2h:3.2ns
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3h:4.0ns
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4h:4.8ns
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5h:5.6ns
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6h:6.4ns
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<b>Default = 0h</b>
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**/
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UINT8 HsioFilterSelN;
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/**
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LFPS filter select for p (filter_sel_p_2_0)
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HSIO_RX_DWORD51 [26:24]
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0h:1.6ns
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1h:2.4ns
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2h:3.2ns
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3h:4.0ns
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4h:4.8ns
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5h:5.6ns
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6h:6.4ns
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<b>Default = 0h</b>
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**/
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UINT8 HsioFilterSelP;
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/**
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Controls the input offset (olfpscfgpullupdwnres_sus_usb_2_0)
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HSIO_RX_DWORD51 [2:0]
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000 Prohibited
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001 45K
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010 Prohibited
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011 31K
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100 36K
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101 36K
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110 36K
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111 36K
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<b>Default = 3h</b>
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**/
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UINT8 HsioOlfpsCfgPullUpDwnRes;
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UINT8 HsioTxDeEmphEnable; ///< Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment, <b>0: Disable</b>; 1: Enable.
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UINT8 HsioTxDownscaleAmpEnable; ///< Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, <b>0: Disable</b>; 1: Enable.
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UINT8 HsioCtrlAdaptOffsetCfgEnable; ///< Enable the write to Signed Magnatude number added to the CTLE code, <b>0: Disable</b>; 1: Enable.
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UINT8 HsioFilterSelNEnable; ///< Enable the write to LFPS filter select for n, <b>0: Disable</b>; 1: Enable.
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UINT8 HsioFilterSelPEnable; ///< Enable the write to LFPS filter select for p, <b>0: Disable</b>; 1: Enable.
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UINT8 HsioOlfpsCfgPullUpDwnResEnable; ///< Enable the write to olfpscfgpullupdwnres, <b>0: Disable</b>; 1: Enable.
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/**
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USB 3.0 TX Output - Unique Transition Bit Scale for rate 3 (rate3UniqTranScale)
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HSIO_TX_DWORD9[6:0]
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<b>Default = 4Ch</b>
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**/
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UINT8 HsioTxRate3UniqTran;
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/**
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USB 3.0 TX Output -Unique Transition Bit Scale for rate 2 (rate2UniqTranScale)
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HSIO_TX_DWORD9[14:8]
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<b>Default = 4Ch</b>
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**/
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UINT8 HsioTxRate2UniqTran;
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/**
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USB 3.0 TX Output - Unique Transition Bit Scale for rate 1 (rate1UniqTranScale)
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HSIO_TX_DWORD9[22:16]
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<b>Default = 4Ch</b>
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**/
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UINT8 HsioTxRate1UniqTran;
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/**
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USB 3.0 TX Output - Unique Transition Bit Scale for rate 0 (rate0UniqTranScale)
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HSIO_TX_DWORD9[30:24]
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<b>Default = 4Ch</b>
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**/
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UINT8 HsioTxRate0UniqTran;
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UINT8 HsioTxRate3UniqTranEnable; ///< Enable the write to USB 3.0 TX Unique Transition Bit Mode for rate 3, <b>0: Disable</b>; 1: Enable.
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UINT8 HsioTxRate2UniqTranEnable; ///< Enable the write to USB 3.0 TX Unique Transition Bit Mode for rate 2, <b>0: Disable</b>; 1: Enable.
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UINT8 HsioTxRate1UniqTranEnable; ///< Enable the write to USB 3.0 TX Unique Transition Bit Mode for rate 1, <b>0: Disable</b>; 1: Enable.
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UINT8 HsioTxRate0UniqTranEnable; ///< Enable the write to USB 3.0 TX Unique Transition Bit Mode for rate 0, <b>0: Disable</b>; 1: Enable.
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} HSIO_PARAMETERS;
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/**
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Structure for holding USB3 tuning parameters
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<b>Revision 1</b>:
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- Initial version.
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<b>Revision 2</b>:
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- USB 3.0 TX Output Unique Transition Bit Scale policies added
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**/
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typedef struct {
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CONFIG_BLOCK_HEADER Header; ///< Config Block Header
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/**
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These members describe whether the USB3 Port N of PCH is enabled by platform modules.
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**/
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HSIO_PARAMETERS Port[MAX_USB3_PORTS];
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} USB3_HSIO_CONFIG;
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#pragma pack (pop)
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#endif // _USB3_HSIO_CONFIG_H_
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