/** @file
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USB2 PHY configuration policy
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Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _USB2_PHY_CONFIG_H_
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#define _USB2_PHY_CONFIG_H_
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#include <UsbConfig.h>
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#define USB2_PHY_CONFIG_REVISION 1
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extern EFI_GUID gUsb2PhyConfigGuid;
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#pragma pack (push,1)
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/**
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This structure configures per USB2 AFE settings.
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It allows to setup the port electrical parameters.
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**/
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typedef struct {
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/** Per Port HS Preemphasis Bias (PERPORTPETXISET)
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000b - 0mV
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001b - 11.25mV
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010b - 16.9mV
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011b - 28.15mV
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100b - 28.15mV
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101b - 39.35mV
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110b - 45mV
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111b - 56.3mV
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**/
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UINT8 Petxiset;
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/** Per Port HS Transmitter Bias (PERPORTTXISET)
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000b - 0mV
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001b - 11.25mV
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010b - 16.9mV
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011b - 28.15mV
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100b - 28.15mV
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101b - 39.35mV
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110b - 45mV
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111b - 56.3mV
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**/
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UINT8 Txiset;
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/**
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Per Port HS Transmitter Emphasis (IUSBTXEMPHASISEN)
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00b - Emphasis OFF
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01b - De-emphasis ON
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10b - Pre-emphasis ON
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11b - Pre-emphasis & De-emphasis ON
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**/
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UINT8 Predeemp;
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/**
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Per Port Half Bit Pre-emphasis (PERPORTTXPEHALF)
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1b - half-bit pre-emphasis
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0b - full-bit pre-emphasis
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**/
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UINT8 Pehalfbit;
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} USB2_PHY_PARAMETERS;
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/**
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This structure holds info on how to tune electrical parameters of USB2 ports based on board layout
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<b>Revision 1</b>:
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- Initial version.
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**/
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typedef struct {
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CONFIG_BLOCK_HEADER Header; ///< Config Block Header
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/**
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This structure configures per USB2 port physical settings.
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It allows to setup the port location and port length, and configures the port strength accordingly.
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Changing this policy values from default ones may require disabling USB2 PHY Sus Well Power Gating
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through Usb2PhySusPgEnable on PCH-LP
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**/
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USB2_PHY_PARAMETERS Port[MAX_USB2_PORTS];
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} USB2_PHY_CONFIG;
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#pragma pack (pop)
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#endif // _USB2_PHY_CONFIG_H_
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