/** @file
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Rst policy
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Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _RST_CONFIG_H_
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#define _RST_CONFIG_H_
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#include <PchLimits.h>
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#include <ConfigBlock.h>
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#define RST_CONFIG_REVISION 1
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extern EFI_GUID gRstConfigGuid;
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#pragma pack (push,1)
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typedef enum {
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SataOromDelay2sec,
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SataOromDelay4sec,
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SataOromDelay6sec,
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SataOromDelay8sec
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} SATA_OROM_DELAY;
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/**
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This structure describes the details of Intel RST for PCIe Storage remapping
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Note: In order to use this feature, Intel RST Driver is required
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**/
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typedef struct {
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/**
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This member describes whether or not the Intel RST for PCIe Storage remapping should be enabled. <b>0: Disable</b>; 1: Enable.
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Note 1: If Sata Controller is disabled, PCIe Storage Remapping should be disabled as well
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Note 2: If PCIe Storage remapping is enabled, the PCH integrated AHCI controllers Class Code is configured as RAID
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**/
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UINT32 Enable : 1;
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/**
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Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, <b>0 = autodetect</b>)
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The supported ports for PCIe Storage remapping is different depend on the platform and cycle router
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**/
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UINT32 RstPcieStoragePort : 5;
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/**
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PCIe Storage Device Reset Delay in milliseconds (ms), which it guarantees such delay gap is fulfilled
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before PCIe Storage Device configuration space is accessed after an reset caused by the link disable and enable step.
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Default value is <b>100ms</b>.
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**/
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UINT32 DeviceResetDelay : 8;
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UINT32 RsvdBits0 : 18; ///< Reserved bits
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} RST_HARDWARE_REMAPPED_STORAGE_CONFIG;
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/**
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Rapid Storage Technology settings.
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<b>Revision 1</b>:
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- Initial version.
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**/
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typedef struct {
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CONFIG_BLOCK_HEADER Header; ///< Config Block Header
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UINT32 Raid0 : 1; ///< 0 : Disable; <b>1 : Enable</b> RAID0
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UINT32 Raid1 : 1; ///< 0 : Disable; <b>1 : Enable</b> RAID1
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UINT32 Raid10 : 1; ///< 0 : Disable; <b>1 : Enable</b> RAID10
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UINT32 Raid5 : 1; ///< 0 : Disable; <b>1 : Enable</b> RAID5
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UINT32 Irrt : 1; ///< 0 : Disable; <b>1 : Enable</b> Intel Rapid Recovery Technology
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UINT32 OromUiBanner : 1; ///< 0 : Disable; <b>1 : Enable</b> OROM UI and BANNER
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UINT32 OromUiDelay : 2; ///< <b>00b : 2 secs</b>; 01b : 4 secs; 10b : 6 secs; 11 : 8 secs (see : SATA_OROM_DELAY)
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UINT32 HddUnlock : 1; ///< 0 : Disable; <b>1 : Enable</b>. Indicates that the HDD password unlock in the OS is enabled
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UINT32 LedLocate : 1; ///< 0 : Disable; <b>1 : Enable</b>. Indicates that the LED/SGPIO hardware is attached and ping to locate feature is enabled on the OS
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UINT32 IrrtOnly : 1; ///< 0 : Disable; <b>1 : Enable</b>. Allow only IRRT drives to span internal and external ports
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UINT32 SmartStorage : 1; ///< 0 : Disable; <b>1 : Enable</b> RST Smart Storage caching Bit
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UINT32 LegacyOrom : 1; ///< <b>0 : Disable</b>; 1 : Enable RST Legacy OROM
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UINT32 OptaneMemory : 1; ///< 0: Disable; <b>1: Enable</b> RST Optane(TM) Memory
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UINT32 CpuAttachedStorage : 1; ///< 0: Disable; <b>1: Enable</b> CPU Attached Storage
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UINT32 RsvdBits0 : 17; ///< Reserved Bits
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/**
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This member describes the details of implementation of Intel RST for PCIe Storage remapping (Intel RST Driver is required)
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Note: RST for PCIe Sorage remapping is supported only for first SATA controller if more controllers are available
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**/
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RST_HARDWARE_REMAPPED_STORAGE_CONFIG HardwareRemappedStorageConfig[PCH_MAX_RST_PCIE_STORAGE_CR];
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} RST_CONFIG;
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#pragma pack (pop)
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#endif
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