/** @file
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Power Management policy
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Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _PM_CONFIG_H_
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#define _PM_CONFIG_H_
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#include <ConfigBlock.h>
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#define PM_CONFIG_REVISION 2
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extern EFI_GUID gPmConfigGuid;
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#pragma pack (push,1)
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/**
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This structure allows to customize PCH wake up capability from S5 or DeepSx by WOL, LAN, PCIE wake events.
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**/
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typedef struct {
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/**
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Corresponds to the PME_B0_S5_DIS bit in the General PM Configuration B (GEN_PMCON_B) register.
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When set to 1, this bit blocks wake events from PME_B0_STS in S5, regardless of the state of PME_B0_EN.
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When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1. <b>0: Disable</b>; 1: Enable.
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**/
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UINT32 PmeB0S5Dis : 1;
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UINT32 WolEnableOverride : 1; ///< Corresponds to the "WOL Enable Override" bit in the General PM Configuration B (GEN_PMCON_B) register. 0: Disable; <b>1: Enable</b>.
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UINT32 PcieWakeFromDeepSx : 1; ///< Determine if enable PCIe to wake from deep Sx. <b>0: Disable</b>; 1: Enable.
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UINT32 WoWlanEnable : 1; ///< Determine if WLAN wake from Sx, corresponds to the "HOST_WLAN_PP_EN" bit in the PWRM_CFG3 register. <b>0: Disable</b>; 1: Enable.
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UINT32 WoWlanDeepSxEnable : 1; ///< Determine if WLAN wake from DeepSx, corresponds to the "DSX_WLAN_PP_EN" bit in the PWRM_CFG3 register. <b>0: Disable</b>; 1: Enable.
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UINT32 LanWakeFromDeepSx : 1; ///< Determine if enable LAN to wake from deep Sx. 0: Disable; <b>1: Enable</b>.
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UINT32 RsvdBits0 : 26;
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} PCH_WAKE_CONFIG;
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typedef enum {
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PchDeepSxPolDisable,
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PchDpS5BatteryEn,
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PchDpS5AlwaysEn,
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PchDpS4S5BatteryEn,
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PchDpS4S5AlwaysEn,
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PchDpS3S4S5BatteryEn,
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PchDpS3S4S5AlwaysEn
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} PCH_DEEP_SX_CONFIG;
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typedef enum {
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PchSlpS360us = 1,
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PchSlpS31ms,
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PchSlpS350ms,
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PchSlpS32s
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} PCH_SLP_S3_MIN_ASSERT;
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typedef enum {
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PchSlpS4PchTime, ///< The time defined in PCH EDS Power Sequencing and Reset Signal Timings table
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PchSlpS41s,
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PchSlpS42s,
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PchSlpS43s,
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PchSlpS44s
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} PCH_SLP_S4_MIN_ASSERT;
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typedef enum {
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PchSlpSus0ms = 1,
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PchSlpSus500ms,
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PchSlpSus1s,
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PchSlpSus4s,
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} PCH_SLP_SUS_MIN_ASSERT;
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typedef enum {
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PchSlpA0ms = 1,
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PchSlpA4s,
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PchSlpA98ms,
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PchSlpA2s,
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} PCH_SLP_A_MIN_ASSERT;
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typedef enum {
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S0ixDisQNoChange,
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S0ixDisQDciOob,
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S0ixDisQUsb2Dbc,
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S0ixDisQMax,
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} S0IX_DISQ_PROBE_TYPE;
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/**
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Low Power Mode Enable config.
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Used to configure if respective S0i2/3 sub-states are to be supported
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by the platform. Each bit corresponds to one LPM state - LPMx->BITx.
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Some sub-states will require external FETs controlled by EXT_PWR_GATE#/EXT_PWR_GATE2# pins
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to gate v1p05-PHY or v1p05-IS supplies
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**/
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typedef union {
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struct {
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UINT32 S0i2p0En : 1; ///< LPM0 - S0i2.0 Enable
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UINT32 S0i2p1En : 1; ///< LPM1 - S0i2.1 Enable
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/**
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LPM2 - S0i2.2 Enable.
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Requires EXT_PWR_GATE# controlled FET to gate v1p05 PHY.
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Refer to V1p05PhyExtFetControlEn.
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**/
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UINT32 S0i2p2En : 1;
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UINT32 S0i3p0En : 1; ///< LPM3 - S0i3.0 Enable
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UINT32 S0i3p1En : 1; ///< LPM4 - S0i3.1 Enable
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UINT32 S0i3p2En : 1; ///< LPM5 - S0i3.2 Enable
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/**
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LPM5 - S0i3.3 Enable.
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Requires EXT_PWR_GATE# controlled FET to gate v1p05 PHY.
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Refer to V1p05PhyExtFetControlEn.
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**/
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UINT32 S0i3p3En : 1;
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/**
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LPM7 - S0i3.4 Enable.
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Requires EXT_PWR_GATE2# controlled FET to gate v1p05-SRAM/ISCLK.
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Refer to V1p05IsExtFetControlEn.
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**/
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UINT32 S0i3p4En : 1;
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UINT32 Reserved : 24; ///< Reserved
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} Field;
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UINT32 Val;
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} PMC_LPM_S0IX_SUB_STATE_EN;
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/**
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Description of Global Reset Trigger/Event Mask register
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**/
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typedef union {
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struct {
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UINT32 Reserved1 : 1;
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UINT32 Pbo : 1;
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UINT32 PmcUncErr : 1;
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UINT32 PchThrm : 1;
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UINT32 MePbo : 1;
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UINT32 CpuThrm : 1;
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UINT32 Megbl : 1;
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UINT32 LtReset : 1;
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UINT32 PmcWdt : 1;
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UINT32 MeWdt : 1;
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UINT32 PmcFw : 1;
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UINT32 PchpwrFlr : 1;
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UINT32 SyspwrFlr : 1;
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UINT32 Reserved2 : 1;
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UINT32 MiaUxsErr : 1;
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UINT32 MiaUxErr : 1;
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UINT32 CpuThrmWdt : 1;
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UINT32 MeUncErr : 1;
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UINT32 AdrGpio : 1;
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UINT32 OcwdtNoicc : 1;
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UINT32 OcwdtIcc : 1;
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UINT32 CseHecUncErr : 1;
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UINT32 PmcSramUncErr : 1;
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UINT32 PmcIromParity : 1;
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UINT32 PmcRfFusaErr : 1;
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UINT32 Reserved3 : 4;
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UINT32 PpbrParityErr : 1;
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UINT32 Reserved4 : 2;
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} Field;
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UINT32 Value;
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} PMC_GLOBAL_RESET_MASK;
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/**
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The PCH_PM_CONFIG block describes expected miscellaneous power management settings.
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The PowerResetStatusClear field would clear the Power/Reset status bits, please
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set the bits if you want PCH Init driver to clear it, if you want to check the
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status later then clear the bits.
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<b>Revision 1</b>:
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- Initial version.
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<b>Revision 2</b>
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- Added C10DynamicThresholdAdjustment
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**/
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typedef struct {
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CONFIG_BLOCK_HEADER Header; ///< Config Block Header
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PCH_WAKE_CONFIG WakeConfig; ///< Specify Wake Policy
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UINT32 PchDeepSxPol : 4; ///< Deep Sx Policy. Refer to PCH_DEEP_SX_CONFIG for each value. Default is <b>PchDeepSxPolDisable</b>.
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UINT32 PchSlpS3MinAssert : 4; ///< SLP_S3 Minimum Assertion Width Policy. Refer to PCH_SLP_S3_MIN_ASSERT for each value. Default is <b>PchSlpS350ms</b>.
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UINT32 PchSlpS4MinAssert : 4; ///< SLP_S4 Minimum Assertion Width Policy. Refer to PCH_SLP_S4_MIN_ASSERT for each value. Default is <b>PchSlpS44s</b>.
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UINT32 PchSlpSusMinAssert : 4; ///< SLP_SUS Minimum Assertion Width Policy. Refer to PCH_SLP_SUS_MIN_ASSERT for each value. Default is <b>PchSlpSus4s</b>.
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UINT32 PchSlpAMinAssert : 4; ///< SLP_A Minimum Assertion Width Policy. Refer to PCH_SLP_A_MIN_ASSERT for each value. Default is <b>PchSlpA2s</b>.
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UINT32 RsvdBits0 : 12;
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/**
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This member describes whether or not the LPC ClockRun feature of PCH should
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be enabled. <b>0: Disable</b>; 1: Enable
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**/
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UINT32 SlpStrchSusUp : 1; ///< <b>0: Disable</b>; 1: Enable SLP_X Stretching After SUS Well Power Up
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/**
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Enable/Disable SLP_LAN# Low on DC Power. 0: Disable; <b>1: Enable</b>.
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Configure On DC PHY Power Diable according to policy SlpLanLowDc.
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When this is enabled, SLP_LAN# will be driven low when ACPRESENT is low.
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This indicates that LAN PHY should be powered off on battery mode.
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This will override the DC_PP_DIS setting by WolEnableOverride.
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**/
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UINT32 SlpLanLowDc : 1;
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/**
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PCH power button override period.
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000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s
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<b>Default is 0: 4s</b>
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**/
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UINT32 PwrBtnOverridePeriod : 3;
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/**
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<b>(Test)</b>
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Disable/Enable PCH to CPU enery report feature. <b>0: Disable</b>; 1: Enable.
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Enery Report is must have feature. Wihtout Energy Report, the performance report
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by workloads/benchmarks will be unrealistic because PCH's energy is not being accounted
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in power/performance management algorithm.
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If for some reason PCH energy report is too high, which forces CPU to try to reduce
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its power by throttling, then it could try to disable Energy Report to do first debug.
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This might be due to energy scaling factors are not correct or the LPM settings are not
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kicking in.
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**/
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UINT32 DisableEnergyReport : 1;
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/**
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When set to Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit.
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When set to Enable, PCH will not pull down AC_PRESENT.
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This setting is ignored when DeepSx is not supported.
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Default is <b>0:Disable</b>
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**/
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UINT32 DisableDsxAcPresentPulldown : 1;
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/**
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Power button native mode disable.
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While FALSE, the PMC's power button logic will act upon the input value from the GPIO unit, as normal.
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While TRUE, this will result in the PMC logic constantly seeing the power button as de-asserted.
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<b>Default is FALSE.</b>
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**/
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UINT32 DisableNativePowerButton : 1;
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UINT32 MeWakeSts : 1; ///< Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register. 0: Disable; <b>1: Enable</b>.
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UINT32 WolOvrWkSts : 1; ///< Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register. 0: Disable; <b>1: Enable</b>.
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/*
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Set true to enable TCO timer.
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When FALSE, it disables PCH ACPI timer, and stops TCO timer.
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@note: This will have significant power impact when it's enabled.
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If TCO timer is disabled, uCode ACPI timer emulation must be enabled,
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and WDAT table must not be exposed to the OS.
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<b>0: Disable</b>, 1: Enable
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*/
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UINT32 EnableTcoTimer : 1;
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/*
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When VRAlert# feature pin is enabled and its state is '0',
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the PMC requests throttling to a T3 Tstate to the PCH throttling unit.
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<b>0: Disable</b>; 1: Enable.
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*/
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UINT32 VrAlert : 1;
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/**
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Decide if PS_ON is to be enabled. This is available on desktop only.
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PS_ON is a new C10 state from the CPU on desktop SKUs that enables a
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lower power target that will be required by the California Energy
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Commission (CEC). When FALSE, PS_ON is to be disabled.}
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<b>0: Disable</b>; 1: Enable.
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**/
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UINT32 PsOnEnable : 1;
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/**
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Enable/Disable platform support for CPU_C10_GATE# pin to control gating
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of CPU VccIO and VccSTG rails instead of SLP_S0# pin. This policy needs
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to be set if board design includes support for CPU_C10_GATE# pin.
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0: Disable; <b>1: Enable</b>
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**/
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UINT32 CpuC10GatePinEnable : 1;
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/**
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Control whether to enable PMC debug messages to Trace Hub.
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When Enabled, PMC HW will send debug messages to trace hub;
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When Disabled, PMC HW will never send debug meesages to trace hub.
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@note: When enabled, system may not enter S0ix
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<b>0: Disable</b>; 1: Enable.
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**/
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UINT32 PmcDbgMsgEn : 1;
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/**
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Enable/Disable ModPHY SUS Power Domain Dynamic Gating.
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EXT_PWR_GATE# signal (if supported on platform) can be used to
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control external FET for power gating ModPHY
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@note: This setting is not supported and ignored on PCH-H
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0: Disable; <b>1: Enable</b>.
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**/
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UINT32 ModPhySusPgEnable : 1;
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/**
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<b>(Test)</b>
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This policy option enables USB2 PHY SUS Well Power Gating functionality.
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@note: This setting is not supported and ignored on PCH-H
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0: disable USB2 PHY SUS Well Power Gating
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<b>1: enable USB2 PHY SUS Well Power Gating</b>
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**/
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UINT32 Usb2PhySusPgEnable : 1;
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/**
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Enable Os Idle Mode.
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0: Disable; <b>1: Enable</b>.
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**/
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UINT32 OsIdleEnable : 1;
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/**
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Enable control using EXT_PWR_GATE# pin of external FET
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to power gate v1p05-PHY
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<b>0: Disable</b>; 1: Enable.
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**/
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UINT32 V1p05PhyExtFetControlEn : 1;
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/**
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Enable control using EXT_PWR_GATE2# pin of external FET
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to power gate v1p05-IS supply
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<b>0: Disable</b>; 1: Enable.
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**/
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UINT32 V1p05IsExtFetControlEn : 1;
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/**
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Enable/Disable the Low Power Mode Host S0ix Auto-Demotion
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feature. This feature enables the PMC to autonomously manage
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the deepest allowed S0ix substate to combat thrashing between
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power management states.
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0: Disable; <b>1: Enable</b>.
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**/
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UINT32 S0ixAutoDemotion : 1;
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/**
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Enable/Disable Latch Events C10 Exit. When this bit is set to 1,
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SLP_S0# entry events in SLP_S0_DEBUG_REGx registers are captured
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on C10 exit (instead of C10 entry which is default)
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<b>0: Disable</b>; 1: Enable.
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**/
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UINT32 LatchEventsC10Exit : 1;
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UINT32 RsvdBits1 : 10;
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/*
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Power button debounce configuration
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Debounce time can be specified in microseconds. Only certain values according
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to below formula are supported:
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DebounceTime = (2 ^ PADCFG_DW2.DEBOUNCE)*(glitch filter clock period).
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RTC clock with f = 32 KHz is used for glitch filter.
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DebounceTime = (2 ^ PADCFG_DW2.DEBOUNCE)*(31.25 us).
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Supported DebounceTime values are following:
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DebounceTime = 0 -> Debounce feature disabled
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DebounceTime > 0 && < 250us -> Not supported
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DebounceTime = 250us - 1024000us -> Supported range (DebounceTime = 250us * 2^n)
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For values not supported by HW, they will be rounded down to closest supported one
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<b>Default is 0</b>
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*/
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UINT32 PowerButtonDebounce;
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/**
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Reset Power Cycle Duration could be customized in the unit of second. Please refer to EDS
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for all support settings. PCH HW default is 4 seconds, and range is 1~4 seconds, where
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<b>0 is default</b>, 1 is 1 second, 2 is 2 seconds, ... 4 is 4 seconds.
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And make sure the setting correct, which never less than the following register.
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- GEN_PMCON_B.SLP_S3_MIN_ASST_WDTH
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- GEN_PMCON_B.SLP_S4_MIN_ASST_WDTH
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- PWRM_CFG.SLP_A_MIN_ASST_WDTH
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- PWRM_CFG.SLP_LAN_MIN_ASST_WDTH
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**/
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UINT8 PchPwrCycDur;
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/**
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Specifies the Pcie Pll Spread Spectrum Percentage
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The value of this policy is in 1/10th percent units.
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Valid spread range is 0-20. A value of 0xFF is reserved for AUTO.
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A value of 0 is SSC of 0.0%. A value of 20 is SSC of 2.0%
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The default is <b>0xFF: AUTO - No BIOS override</b>.
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**/
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UINT8 PciePllSsc;
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/**
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Tells BIOS to enable C10 dynamic threshold adjustment mode.
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BIOS will only attemt to enable it on PCH SKUs which support it.
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**/
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UINT8 C10DynamicThresholdAdjustment;
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UINT8 Rsvd0[1]; ///< Reserved bytes
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/**
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<b>(Test)</b>
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Low Power Mode Enable/Disable config.
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Configure if respective S0i2/3 sub-states are to be supported
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by the platform. By default all sub-states are enabled but
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for test purpose respective states can be disabled.
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<b>Default is 0xFF</b>
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**/
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PMC_LPM_S0IX_SUB_STATE_EN LpmS0ixSubStateEnable;
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/*
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Set true to enable Timed GPIO 0 timer.
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<b>0: Disable</b>, 1: Enable
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*/
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UINT32 EnableTimedGpio0 : 1;
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/*
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Set true to enable Timed GPIO 1 timer.
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<b>0: Disable</b>, 1: Enable
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*/
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UINT32 EnableTimedGpio1 : 1;
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UINT32 Rsvdbits : 30;
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/**
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Set true to enable override of Global Reset Event/Trigger masks.
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Values from GlobalResetTriggerMask and GlobalResetEventMask will
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be used as override value.
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<b>0: Disable</b>, 1: Enable
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**/
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UINT8 GlobalResetMasksOverride;
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UINT8 Rsvd1[3]; ///< Reserved bytes
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/*
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Mask for enabling Global Reset Trigger prevention
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*/
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PMC_GLOBAL_RESET_MASK GlobalResetTriggerMask;
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/*
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Mask for enabling Global Reset Event prevention
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*/
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PMC_GLOBAL_RESET_MASK GlobalResetEventMask;
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} PCH_PM_CONFIG;
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#pragma pack (pop)
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#endif // _PM_CONFIG_H_
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