/** @file
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PCIe Config Block
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Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _PCIE_CONFIG_H_
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#define _PCIE_CONFIG_H_
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#include <CpuPcieInfo.h>
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#define PCIE_CONFIG_REVISION 3
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/*
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<b>Revision 2< / b>:
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FomsCp - Deprecated
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<b>Revision 3< / b>:
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Added PCIE_EQ_PARAM HwEqGen3CoeffList for all CPU_PCIE_MAX_ROOT_PORTS
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Added PCIE_EQ_PARAM HwEqGen4CoeffList for all CPU_PCIE_MAX_ROOT_PORTS
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Added PCIE_EQ_PARAM HwEqGen5CoeffList for all CPU_PCIE_MAX_ROOT_PORTS
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*/
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extern EFI_GUID gPcieConfigGuid;
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#pragma pack (push,1)
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enum PCIE_COMPLETION_TIMEOUT {
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PcieCompletionTO_Default,
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PcieCompletionTO_50_100us,
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PcieCompletionTO_1_10ms,
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PcieCompletionTO_16_55ms,
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PcieCompletionTO_65_210ms,
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PcieCompletionTO_260_900ms,
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PcieCompletionTO_1_3P5s,
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PcieCompletionTO_4_13s,
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PcieCompletionTO_17_64s,
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PcieCompletionTO_Disabled
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};
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enum PCIE_SPEED {
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PcieAuto,
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PcieGen1,
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PcieGen2,
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PcieGen3,
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PcieGen4
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};
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/**
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Represent lane specific PCIe Gen3 equalization parameters.
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**/
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typedef struct {
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UINT8 Cm; ///< Coefficient C-1
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UINT8 Cp; ///< Coefficient C+1
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UINT8 Rsvd0[2]; ///< Reserved bytes
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} PCIE_EQ_PARAM;
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typedef struct {
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UINT16 LtrMaxSnoopLatency; ///< <b>(Test)</b> Latency Tolerance Reporting, Max Snoop Latency.
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UINT16 LtrMaxNoSnoopLatency; ///< <b>(Test)</b> Latency Tolerance Reporting, Max Non-Snoop Latency.
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UINT8 SnoopLatencyOverrideMode; ///< <b>(Test)</b> Latency Tolerance Reporting, Snoop Latency Override Mode.
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UINT8 SnoopLatencyOverrideMultiplier; ///< <b>(Test)</b> Latency Tolerance Reporting, Snoop Latency Override Multiplier.
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UINT16 SnoopLatencyOverrideValue; ///< <b>(Test)</b> Latency Tolerance Reporting, Snoop Latency Override Value.
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UINT8 NonSnoopLatencyOverrideMode; ///< <b>(Test)</b> Latency Tolerance Reporting, Non-Snoop Latency Override Mode.
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UINT8 NonSnoopLatencyOverrideMultiplier; ///< <b>(Test)</b> Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier.
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UINT16 NonSnoopLatencyOverrideValue; ///< <b>(Test)</b> Latency Tolerance Reporting, Non-Snoop Latency Override Value.
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UINT8 LtrConfigLock; ///< <b>0: Disable</b>; 1: Enable.
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UINT8 ForceLtrOverride;
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UINT16 RsvdByte1;
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} PCIE_LTR_CONFIG;
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/**
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Specifies the form factor that the slot
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implements. For custom form factors that
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do not require any special handling please
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set PcieFormFactorOther.
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**/
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typedef enum {
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PcieFormFactorOther = 0,
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PcieFormFactorCem,
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PcieFormFactorMiniPci,
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PcieFormFactorM2,
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PcieFormFactorOcuLink,
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PcieFormFactorExpressModule, // Also known as Server IO module(SIOM)
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PcieFormFactorExpressCard,
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PcieFormFactorU2 // Also known as SF-8639
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} PCIE_FORM_FACTOR;
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//Note: This structure will be expanded to hold all common PCIe policies between SA and PCH RootPort
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typedef struct {
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UINT32 HotPlug : 1; ///< Indicate whether the root port is hot plug available. <b>0: Disable</b>; 1: Enable.
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UINT32 PmSci : 1; ///< Indicate whether the root port power manager SCI is enabled. 0: Disable; <b>1: Enable</b>.
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UINT32 TransmitterHalfSwing : 1; ///< Indicate whether the Transmitter Half Swing is enabled. <b>0: Disable</b>; 1: Enable.
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UINT32 AcsEnabled : 1; ///< Indicate whether the ACS is enabled. 0: Disable; <b>1: Enable</b>.
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//
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// Error handlings
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//
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UINT32 AdvancedErrorReporting : 1; ///< Indicate whether the Advanced Error Reporting is enabled. <b>0: Disable</b>; 1: Enable.
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UINT32 UnsupportedRequestReport : 1; ///< Indicate whether the Unsupported Request Report is enabled. <b>0: Disable</b>; 1: Enable.
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UINT32 FatalErrorReport : 1; ///< Indicate whether the Fatal Error Report is enabled. <b>0: Disable</b>; 1: Enable.
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UINT32 NoFatalErrorReport : 1; ///< Indicate whether the No Fatal Error Report is enabled. <b>0: Disable</b>; 1: Enable.
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UINT32 CorrectableErrorReport : 1; ///< Indicate whether the Correctable Error Report is enabled. <b>0: Disable</b>; 1: Enable.
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UINT32 SystemErrorOnFatalError : 1; ///< Indicate whether the System Error on Fatal Error is enabled. <b>0: Disable</b>; 1: Enable.
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UINT32 SystemErrorOnNonFatalError : 1; ///< Indicate whether the System Error on Non Fatal Error is enabled. <b>0: Disable</b>; 1: Enable.
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UINT32 SystemErrorOnCorrectableError : 1; ///< Indicate whether the System Error on Correctable Error is enabled. <b>0: Disable</b>; 1: Enable.
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/**
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Max Payload Size supported, Default <b>128B</b>, see enum CPU_PCIE_MAX_PAYLOAD
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Changes Max Payload Size Supported field in Device Capabilities of the root port.
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**/
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UINT32 MaxPayload : 2;
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UINT32 DpcEnabled : 1; ///< Downstream Port Containment. 0: Disable; <b>1: Enable</b>
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UINT32 RpDpcExtensionsEnabled : 1; ///< RP Extensions for Downstream Port Containment. 0: Disable; <b>1: Enable</b>
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/**
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Indicates how this root port is connected to endpoint. 0: built-in device; <b>1: slot</b>
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Built-in is incompatible with hotplug-capable ports.
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**/
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UINT32 SlotImplemented : 1;
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UINT32 PtmEnabled : 1; ///< Enables PTM capability
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UINT32 SlotPowerLimitScale : 2; ///< <b>(Test)</b> Specifies scale used for slot power limit value. Leave as 0 to set to default. Default is <b>zero</b>.
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UINT32 SlotPowerLimitValue : 12; //< <b>(Test)</b> Specifies upper limit on power supplies by slot. Leave as 0 to set to default. Default is <b>zero</b>.
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/**
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Probe CLKREQ# signal before enabling CLKREQ# based power management.
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Conforming device shall hold CLKREQ# low until CPM is enabled. This feature attempts
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to verify CLKREQ# signal is connected by testing pad state before enabling CPM.
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In particular this helps to avoid issues with open-ended PCIe slots.
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This is only applicable to non hot-plug ports.
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<b>0: Disable</b>; 1: Enable.
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**/
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UINT32 ClkReqDetect : 1;
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/**
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Set if the slot supports manually operated retention latch.
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**/
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UINT32 MrlSensorPresent : 1;
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UINT32 RelaxedOrder : 1;
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UINT32 NoSnoop : 1;
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UINT32 RsvdBits0 : 28; ///< Reserved bits.
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/**
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PCIe Gen3 Equalization Phase 3 Method (see CPU_PCIE_EQ_METHOD).
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0: DEPRECATED, hardware equalization; <b>1: hardware equalization</b>; 4: Fixed Coefficients
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**/
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UINT8 Gen3EqPh3Method;
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UINT8 PhysicalSlotNumber; ///< Indicates the slot number for the root port. Default is the value as root port index.
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UINT8 CompletionTimeout; ///< The completion timeout configuration of the root port (see: CPU_PCIE_COMPLETION_TIMEOUT). Default is <b>PchPcieCompletionTO_Default</b>.
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//
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// Power Management
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//
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UINT8 Aspm; ///< The ASPM configuration of the root port (see: CPU_PCIE_ASPM_CONTROL). Default is <b>PchPcieAspmAutoConfig</b>.
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UINT8 L1Substates; ///< The L1 Substates configuration of the root port (see: CPU_PCIE_L1SUBSTATES_CONTROL). Default is <b>PchPcieL1SubstatesL1_1_2</b>.
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UINT8 LtrEnable; ///< Latency Tolerance Reporting Mechanism. <b>0: Disable</b>; 1: Enable.
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UINT8 EnableCpm; ///< Enables Clock Power Management; even if disabled, CLKREQ# signal can still be controlled by L1 PM substates mechanism
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UINT8 PcieSpeed; ///< Contains speed of PCIe bus (see: PCIE_SPEED)
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/**
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<b>(Test)</b>
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Forces LTR override to be permanent
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The default way LTR override works is:
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rootport uses LTR override values provided by BIOS until connected device sends an LTR message, then it will use values from the message
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This settings allows force override of LTR mechanism. If it's enabled, then:
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rootport will use LTR override values provided by BIOS forever; LTR messages sent from connected device will be ignored
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**/
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PCIE_LTR_CONFIG PcieRpLtrConfig; ///< <b>(Test)</b> Latency Tolerance Reporting Policies including LTR limit and Override
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/**
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The number of milliseconds reference code will wait for link to exit Detect state for enabled ports
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before assuming there is no device and potentially disabling the port.
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It's assumed that the link will exit detect state before root port initialization (sufficient time
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elapsed since PLTRST de-assertion) therefore default timeout is zero. However this might be useful
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if device power-up seqence is controlled by BIOS or a specific device requires more time to detect.
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In case of non-common clock enabled the default timout is 15ms.
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<b>Default: 0</b>
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**/
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UINT16 DetectTimeoutMs;
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UINT8 FormFactor; // Please check PCIE_FORM_FACTOR for supported values
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UINT8 Reserved;
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} PCIE_ROOT_PORT_COMMON_CONFIG;
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/**
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PCIe Common Config
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@note This structure will be expanded to hold all common PCIe policies between SA and PCH
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**/
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typedef struct {
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///
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/// This member describes whether Peer Memory Writes are enabled on the platform. <b>0: Disable</b>; 1: Enable.
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///
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UINT32 EnablePeerMemoryWrite : 1;
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/**
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RpFunctionSwap allows BIOS to use root port function number swapping when root port of function 0 is disabled.
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A PCIE device can have higher functions only when Function0 exists. To satisfy this requirement,
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BIOS will always enable Function0 of a device that contains more than 0 enabled root ports.
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- <b>Enabled: One of enabled root ports get assigned to Function0.</b>
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This offers no guarantee that any particular root port will be available at a specific DevNr:FuncNr location
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- Disabled: Root port that corresponds to Function0 will be kept visible even though it might be not used.
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That way rootport - to - DevNr:FuncNr assignment is constant. This option will impact ports 1, 9, 17.
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NOTE: This option will not work if ports 1, 9, 17 are fused or configured for RST PCIe storage or disabled through policy
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In other words, it only affects ports that would become hidden because they have no device connected.
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NOTE: Disabling function swap may have adverse impact on power management. This option should ONLY
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be used when each one of root ports 1, 9, 17:
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- is configured as PCIe and has correctly configured ClkReq signal, or
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- does not own any mPhy lanes (they are configured as SATA or USB)
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**/
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UINT32 RpFunctionSwap : 1;
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/**
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Compliance Test Mode shall be enabled when using Compliance Load Board.
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<b>0: Disable</b>, 1: Enable
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**/
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UINT32 ComplianceTestMode : 1;
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UINT32 RsvdBits0 : 29; ///< Reserved bits
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///
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/// List of coefficients used during equalization (applicable to both software and hardware EQ)
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/// Deprecated Policy
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///
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PCIE_EQ_PARAM HwEqGen3CoeffList[PCIE_HWEQ_COEFFS_MAX];
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} PCIE_COMMON_CONFIG;
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typedef struct {
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PCIE_EQ_PARAM HwEqGen3CoeffList[CPU_PCIE_MAX_ROOT_PORTS][PCIE_HWEQ_COEFFS_MAX];
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PCIE_EQ_PARAM HwEqGen4CoeffList[CPU_PCIE_MAX_ROOT_PORTS][PCIE_HWEQ_COEFFS_MAX];
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} PCIE_COMMON_CONFIG2;
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#pragma pack (pop)
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#endif // _PCIE_CONFIG_H_
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