/** @file
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PCH Pcie root port policy
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Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _PCH_PCIERP_CONFIG_H_
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#define _PCH_PCIERP_CONFIG_H_
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#include <PchLimits.h>
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#include <PcieConfig.h>
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#include <ConfigBlock.h>
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#define PCIE_RP_CONFIG_REVISION 1
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#define PCIE_RP_PREMEM_CONFIG_REVISION 1
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#define PCIE_RP_DXE_CONFIG_REVISION 1
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extern EFI_GUID gPchPcieConfigGuid;
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extern EFI_GUID gPcieRpPreMemConfigGuid;
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#pragma pack (push,1)
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#define PCIE_LINK_EQ_COEFFICIENTS_MAX 10
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#define PCIE_LINK_EQ_PRESETS_MAX 11
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typedef enum {
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PchPcieOverrideDisabled = 0,
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PchPcieL1L2Override = 0x01,
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PchPcieL1SubstatesOverride = 0x02,
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PchPcieL1L2AndL1SubstatesOverride = 0x03,
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PchPcieLtrOverride = 0x04
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} PCH_PCIE_OVERRIDE_CONFIG;
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/**
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PCIe device table entry entry
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The PCIe device table is being used to override PCIe device ASPM settings.
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To take effect table consisting of such entries must be instelled as PPI
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on gPchPcieDeviceTablePpiGuid.
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Last entry VendorId must be 0.
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**/
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typedef struct {
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UINT16 VendorId; ///< The vendor Id of Pci Express card ASPM setting override, 0xFFFF means any Vendor ID
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UINT16 DeviceId; ///< The Device Id of Pci Express card ASPM setting override, 0xFFFF means any Device ID
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UINT8 RevId; ///< The Rev Id of Pci Express card ASPM setting override, 0xFF means all steppings
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UINT8 BaseClassCode; ///< The Base Class Code of Pci Express card ASPM setting override, 0xFF means all base class
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UINT8 SubClassCode; ///< The Sub Class Code of Pci Express card ASPM setting override, 0xFF means all sub class
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UINT8 EndPointAspm; ///< Override device ASPM (see: PCH_PCIE_ASPM_CONTROL)
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///< Bit 1 must be set in OverrideConfig for this field to take effect
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UINT16 OverrideConfig; ///< The override config bitmap (see: PCH_PCIE_OVERRIDE_CONFIG).
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/**
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The L1Substates Capability Offset Override. (applicable if bit 2 is set in OverrideConfig)
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This field can be zero if only the L1 Substate value is going to be override.
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**/
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UINT16 L1SubstatesCapOffset;
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/**
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L1 Substate Capability Mask. (applicable if bit 2 is set in OverrideConfig)
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Set to zero then the L1 Substate Capability [3:0] is ignored, and only L1s values are override.
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Only bit [3:0] are applicable. Other bits are ignored.
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**/
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UINT8 L1SubstatesCapMask;
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/**
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L1 Substate Port Common Mode Restore Time Override. (applicable if bit 2 is set in OverrideConfig)
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L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value of 0, but not the L1sTpowerOnValue.
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If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOnScale, and L1sTpowerOnValue are ignored,
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and only L1SubstatesCapOffset is override.
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**/
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UINT8 L1sCommonModeRestoreTime;
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/**
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L1 Substate Port Tpower_on Scale Override. (applicable if bit 2 is set in OverrideConfig)
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L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value of 0, but not the L1sTpowerOnValue.
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If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOnScale, and L1sTpowerOnValue are ignored,
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and only L1SubstatesCapOffset is override.
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**/
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UINT8 L1sTpowerOnScale;
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/**
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L1 Substate Port Tpower_on Value Override. (applicable if bit 2 is set in OverrideConfig)
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L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value of 0, but not the L1sTpowerOnValue.
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If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOnScale, and L1sTpowerOnValue are ignored,
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and only L1SubstatesCapOffset is override.
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**/
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UINT8 L1sTpowerOnValue;
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/**
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SnoopLatency bit definition
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Note: All Reserved bits must be set to 0
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BIT[15] - When set to 1b, indicates that the values in bits 9:0 are valid
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When clear values in bits 9:0 will be ignored
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BITS[14:13] - Reserved
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BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits
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000b - 1 ns
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001b - 32 ns
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010b - 1024 ns
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011b - 32,768 ns
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100b - 1,048,576 ns
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101b - 33,554,432 ns
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110b - Reserved
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111b - Reserved
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BITS[9:0] - Snoop Latency Value. The value in these bits will be multiplied with
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the scale in bits 12:10
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This field takes effect only if bit 3 is set in OverrideConfig.
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**/
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UINT16 SnoopLatency;
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/**
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NonSnoopLatency bit definition
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Note: All Reserved bits must be set to 0
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BIT[15] - When set to 1b, indicates that the values in bits 9:0 are valid
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When clear values in bits 9:0 will be ignored
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BITS[14:13] - Reserved
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BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits
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000b - 1 ns
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001b - 32 ns
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010b - 1024 ns
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011b - 32,768 ns
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100b - 1,048,576 ns
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101b - 33,554,432 ns
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110b - Reserved
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111b - Reserved
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BITS[9:0] - Non Snoop Latency Value. The value in these bits will be multiplied with
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the scale in bits 12:10
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This field takes effect only if bit 3 is set in OverrideConfig.
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**/
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UINT16 NonSnoopLatency;
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/**
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Forces LTR override to be permanent
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The default way LTR override works is:
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rootport uses LTR override values provided by BIOS until connected device sends an LTR message, then it will use values from the message
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This settings allows force override of LTR mechanism. If it's enabled, then:
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rootport will use LTR override values provided by BIOS forever; LTR messages sent from connected device will be ignored
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**/
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UINT8 ForceLtrOverride;
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UINT8 Reserved[3];
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} PCH_PCIE_DEVICE_OVERRIDE;
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///
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/// The values before AutoConfig match the setting of PCI Express Base Specification 1.1, please be careful for adding new feature
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///
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typedef enum {
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PchPcieAspmDisabled,
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PchPcieAspmL0s,
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PchPcieAspmL1,
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PchPcieAspmL0sL1,
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PchPcieAspmAutoConfig,
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PchPcieAspmMax
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} PCH_PCIE_ASPM_CONTROL;
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/**
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Refer to PCH EDS for the PCH implementation values corresponding
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to below PCI-E spec defined ranges
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**/
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typedef enum {
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PchPcieL1SubstatesDisabled,
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PchPcieL1SubstatesL1_1,
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PchPcieL1SubstatesL1_1_2,
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PchPcieL1SubstatesMax
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} PCH_PCIE_L1SUBSTATES_CONTROL;
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enum PCH_PCIE_MAX_PAYLOAD {
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PchPcieMaxPayload128 = 0,
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PchPcieMaxPayload256,
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PchPcieMaxPayloadMax
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};
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typedef enum {
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PcieLinkHardwareEq = 0, ///< Hardware is responsible for performing coefficient/preset search.
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PcieLinkFixedEq ///< No coefficient/preset search is performed. Fixed values are used.
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} PCIE_LINK_EQ_METHOD;
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typedef enum {
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PcieLinkEqPresetMode = 0, ///< Use presets during PCIe link equalization
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PcieLinkEqCoefficientMode ///< Use coefficients during PCIe link equalization
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} PCIE_LINK_EQ_MODE;
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typedef struct {
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UINT32 PreCursor; ///< Pre-cursor coefficient
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UINT32 PostCursor; ///< Post-cursor coefficient
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} PCIE_LINK_EQ_COEFFICIENTS;
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/**
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PCIe Link EQ Platform Settings
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**/
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typedef struct {
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UINT8 PcieLinkEqMethod; ///< Tells BIOS which link EQ method should be used for this port. Please refer to PCIE_LINK_EQ_METHOD for details of supported methods. Default: PcieLinkHardwareEq
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UINT8 PcieLinkEqMode; ///< Tells BIOS which mode should be used for PCIe link EQ. Please refer to PCIE_LINK_EQ_MODE for details of supported modes. Default: depends on SoC
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/**
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Specifies if BIOS should perform local transmitter override during phase 2 of EQ process.
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If enabled value in Ph2LocalTransmitterOverridePreset must be valid.
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<b>0: Disabled</b>; 1: Enabled
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**/
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UINT8 LocalTransmitterOverrideEnable;
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/**
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Tells BIOS how many presets/coefficients should be used during link EQ.
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Entries in the Ph3CoefficientsList or Ph3PresetList(depending on chosen mode) need to be valid up to the number specified in this field.
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**/
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UINT8 Ph3NumberOfPresetsOrCoefficients;
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PCIE_LINK_EQ_COEFFICIENTS Ph3CoefficientsList[PCIE_LINK_EQ_COEFFICIENTS_MAX]; ///< List of the PCIe coefficients to be used during equalization process. Only valid if PcieLinkEqMode is PcieLinkEqCoefficientMode
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UINT32 Ph3PresetList[PCIE_LINK_EQ_PRESETS_MAX]; ///< List of the PCIe preset values to be used during equalization process. Only valid if PcieLinkEqMode is PcieLinkEqPresetMode
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UINT32 Ph1DownstreamPortTransmitterPreset; ///< Specifies the value of the downstream port transmitter preset to be used during phase 1 of the equalization process. Will be applied to all lanes
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UINT32 Ph1UpstreamPortTransmitterPreset; ///< Specifies the value of the upstream port transmitter preset to be used during phase 1 of the equalization process. Will be applied to all lanes
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/**
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Specifies the preset that should be used during local transmitter override during phase 2 of EQ process.
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Used only if LocalTransmitterOverrideEnable is TRUE. Will be applied to all PCIe lanes of the root port.
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Valid up to the PCIE_LINK_EQ_PRESET_MAX value. <b>Default: 0<\b>
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**/
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UINT32 Ph2LocalTransmitterOverridePreset;
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} PCIE_LINK_EQ_PLATFORM_SETTINGS;
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#define PCH_PCIE_NO_SUCH_CLOCK 0xFF
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typedef enum {
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PchClockUsagePchPcie0 = 0,
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PchClockUsagePchPcie1 = 1,
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PchClockUsagePchPcie2 = 2,
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PchClockUsagePchPcie3 = 3,
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PchClockUsagePchPcie4 = 4,
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PchClockUsagePchPcie5 = 5,
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PchClockUsagePchPcie6 = 6,
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PchClockUsagePchPcie7 = 7,
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PchClockUsagePchPcie8 = 8,
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PchClockUsagePchPcie9 = 9,
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PchClockUsagePchPcie10 = 10,
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PchClockUsagePchPcie11 = 11,
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PchClockUsagePchPcie12 = 12,
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PchClockUsagePchPcie13 = 13,
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PchClockUsagePchPcie14 = 14,
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PchClockUsagePchPcie15 = 15,
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PchClockUsagePchPcie16 = 16,
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PchClockUsagePchPcie17 = 17,
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PchClockUsagePchPcie18 = 18,
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PchClockUsagePchPcie19 = 19,
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PchClockUsagePchPcie20 = 20,
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PchClockUsagePchPcie21 = 21,
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PchClockUsagePchPcie22 = 22,
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PchClockUsagePchPcie23 = 23,
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/**
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Quantity of PCH and CPU PCIe ports, as well as their encoding in this enum, may change between
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silicon generations and series. Do not assume that PCH port 0 will be always encoded by 0.
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Instead, it is recommended to use (PchClockUsagePchPcie0 + PchPortIndex) style to be forward-compatible
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**/
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PchClockUsageCpuPcie0 = 0x40,
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PchClockUsageCpuPcie1 = 0x41,
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PchClockUsageCpuPcie2 = 0x42,
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PchClockUsageCpuPcie3 = 0x43,
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PchClockUsageLan = 0x70,
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PchClockUsageUnspecified = 0x80, ///< In use for a purpose not listed above
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PchClockUsageNotUsed = 0xFF
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} PCH_PCIE_CLOCK_USAGE;
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/**
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PCH_PCIE_CLOCK describes PCIe source clock generated by PCH.
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**/
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typedef struct {
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UINT8 Usage; ///< Purpose of given clock (see PCH_PCIE_CLOCK_USAGE). Default: Unused, 0xFF
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UINT8 ClkReq; ///< ClkSrc - ClkReq mapping. Default: 1:1 mapping with Clock numbers
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UINT8 RsvdBytes[2]; ///< Reserved byte
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} PCH_PCIE_CLOCK;
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/**
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The PCH_PCI_EXPRESS_ROOT_PORT_CONFIG describe the feature and capability of each PCH PCIe root port.
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**/
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typedef struct {
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PCIE_ROOT_PORT_COMMON_CONFIG PcieRpCommonConfig; ///an instance of Pcie Common Config
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UINT8 ExtSync; ///< Indicate whether the extended synch is enabled. <b>0: Disable</b>; 1: Enable.
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//
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// Error handlings
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//
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UINT8 SystemErrorEnable; ///< Indicate whether the System Error is enabled. <b>0: Disable</b>; 1: Enable.
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/**
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The Multiple VC (MVC) supports hardware to avoid HoQ block for latency sensitive TC.
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Currently it is only applicable to Root Ports with 2pX4 port configuration with 2 VCs,or
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DMI port configuration with 3 VCs. For Root Ports 2pX4 configuration, two RPs (RP0,
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RP2) shall support two PCIe VCs (VC0 & VC1) and the other RPs (RP1, RP3) shall be
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disabled.
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<b>0: Disable</b>; 1: Enable
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**/
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UINT8 MvcEnabled;
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/**
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Virtual Pin Port is industry standard introduced to PCIe Hot Plug support in systems
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when GPIO pins expansion is needed. It is server specific feature.
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<b>0x00: Default</b>; 0xFF: Disabled
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**/
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UINT8 VppPort;
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UINT8 VppAddress; ///< PCIe Hot Plug VPP SMBus Address. Default is zero.
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UINT8 RsvdBytes0[3]; ///< Reserved bytes
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} PCH_PCIE_ROOT_PORT_CONFIG;
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/**
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The PCH_PCIE_CONFIG block describes the expected configuration of the PCH PCI Express controllers
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<b>Revision 1</b>:
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- Initial version.
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**/
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typedef struct {
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CONFIG_BLOCK_HEADER Header; ///< Config Block Header
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///
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/// These members describe the configuration of each PCH PCIe root port.
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///
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PCIE_COMMON_CONFIG PcieCommonConfig;
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PCH_PCIE_ROOT_PORT_CONFIG RootPort[PCH_MAX_PCIE_ROOT_PORTS];
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PCIE_LINK_EQ_PLATFORM_SETTINGS PcieLinkEqPlatformSettings; ///< Global PCIe link EQ settings that BIOS will use during PCIe link EQ for every port.
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///
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/// <b>0: Use project default equalization settings</b>; 1: Use equalization settings from PcieLinkEqPlatformSettings
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///
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UINT8 OverrideEqualizationDefaults;
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///
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/// <b>(Test)</b> This member describes whether PCIE root port Port 8xh Decode is enabled. <b>0: Disable</b>; 1: Enable.
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///
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UINT8 EnablePort8xhDecode;
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///
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/// <b>(Test)</b> The Index of PCIe Port that is selected for Port8xh Decode (0 Based)
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///
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UINT8 PchPciePort8xhDecodePortIndex;
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UINT8 RsvdBytes0[1];
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} PCH_PCIE_CONFIG;
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/**
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The PCH_PCIE_RP_PREMEM_CONFIG block describes early configuration of the PCH PCI Express controllers
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<b>Revision 1</b>:
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- Initial version.
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**/
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typedef struct {
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CONFIG_BLOCK_HEADER Header; ///< Config Block Header
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/**
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Root Port enabling mask.
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Bit0 presents RP1, Bit1 presents RP2, and so on.
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0: Disable; <b>1: Enable</b>.
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**/
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UINT32 RpEnabledMask;
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/// Configuration of PCIe source clocks
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///
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PCH_PCIE_CLOCK PcieClock[PCH_MAX_PCIE_CLOCKS];
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/**
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Per Controller Bifurcation Configuration
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<b>0: Disabled</b>; 1: 4x1; 2: 1x2_2x1; 3: 2x2; 4: 1x4; 5: 4x2; 6: 1x4_2x2; 7: 2x2_1x4; 8: 2x4; 9: 1x8 (see: PCIE_BIFURCATION_CONFIG)
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**/
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UINT8 Bifurcation[PCH_MAX_PCIE_CONTROLLERS];
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UINT8 Rsvd4[(4 - PCH_MAX_PCIE_CONTROLLERS % 4) % 4];
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} PCH_PCIE_RP_PREMEM_CONFIG;
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/**
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The PCIE_RP_DXE_CONFIG block describes the expected configuration of the PCH PCI Express controllers in DXE phase
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<b>Revision 1</b>:
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- Init version
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**/
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typedef struct {
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CONFIG_BLOCK_HEADER Header; ///< Config Block Header
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/**
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PCIe device override table
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The PCIe device table is being used to override PCIe device ASPM settings.
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And it's only used in DXE phase.
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Please refer to PCH_PCIE_DEVICE_OVERRIDE structure for the table.
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Last entry VendorId must be 0.
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**/
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PCH_PCIE_DEVICE_OVERRIDE *PcieDeviceOverrideTablePtr;
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} PCIE_RP_DXE_CONFIG;
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#pragma pack (pop)
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#endif // _PCH_PCIERP_CONFIG_H_
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