/** @file
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Overclocking Config Block.
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Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _OVERCLOCKING_PREMEM_CONFIG_H_
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#define _OVERCLOCKING_PREMEM_CONFIG_H_
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#define OVERCLOCKING_CONFIG_REVISION 9
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extern EFI_GUID gOverclockingPreMemConfigGuid;
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#pragma pack (push,1)
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//
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// Max number of VF point offset
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//
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#ifndef CPU_OC_MAX_VF_POINTS
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#define CPU_OC_MAX_VF_POINTS 0xF
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#endif
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#ifndef CPU_OC_MAX_CORES
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#define CPU_OC_MAX_CORES 8
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#endif
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/**
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Overclocking Configuration Structure.
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<b>Revision 1</b>:
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- Initial version.
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<b>Revision 2</b>
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- Add PerCoreHtDisable
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<b>Revision 3</b>
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- Add Avx2VoltageScaleFactor and Avx512VoltageScaleFactor
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<b>Revision 4</b>
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- Add CoreVfPointOffsetMode & CoreVfPointOffset & CoreVfPointRatio & CoreVfPointCount
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<b>Revision 5</b>
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- Change OcLock default to 'Enabled'
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<b>Revision 6</b>:
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- Add DisableCoreMask.
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<b>Revision 7</b>
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Add UnlimitedIccMax
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<b>Revision 8</b>
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- Add PerCoreRatioOverride and PerCoreRatio for Per Core PState overclocking.
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<b>Revision 9</b>
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- Add VccInVoltageOverride.
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**/
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typedef struct {
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CONFIG_BLOCK_HEADER Header; ///< Config Block Header
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/**
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Overclocking support. This controls whether OC mailbox transactions are sent.
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If disabled, all policies in this config block besides OcSupport and OcLock will be ignored.
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<b>0: Disable</b>;
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1: Enable.
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@note If PcdOverclockEnable is disabled, this should also be disabled.
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**/
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UINT32 OcSupport : 1;
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UINT32 OcLock : 1; ///< If enabled, sets OC lock bit in MSR 0x194[20], locking the OC mailbox and other OC configuration settings.; 0: Disable; <b>1: Enable (Lock)</b>.
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/**
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Core voltage mode, specifies which voltage mode the processor will be operating.
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<b>0: Adaptive Mode</b> allows the processor to interpolate a voltage curve when beyond fused P0 range;
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1: Override, sets one voltage for for the entire frequency range, Pn-P0.
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**/
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UINT32 CoreVoltageMode : 1;
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UINT32 CorePllVoltageOffset : 6; ///< Core PLL voltage offset. <b>0: No offset</b>. Range 0-63 in 17.5mv units.
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UINT32 Avx2RatioOffset : 5; ///< AVX2 Ratio Offset. <b>0: No offset</b>. Range is 0-31. Used to lower the AVX ratio to maximize possible ratio for SSE workload.
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UINT32 Avx3RatioOffset : 5; ///< AVX3 Ratio Offset. <b>0: No offset</b>. Range is 0-31. Used to lower the AVX3 ratio to maximize possible ratio for SSE workload.
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UINT32 BclkAdaptiveVoltage : 1; ///< Bclk Adaptive Voltage enable/disable. <b>0: Disabled</b>, 1: Enabled. When enabled, the CPU V/F curves are aware of BCLK frequency when calculated.
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/**
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Ring Downbin enable/disable.
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When enabled, the CPU will force the ring ratio to be lower than the core ratio.
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Disabling will allow the ring and core ratios to run at the same frequency.
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Uses OC Mailbox command 0x19.
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0: Disables Ring Downbin feature. <b>1: Enables Ring downbin feature.</b>
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**/
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UINT32 RingDownBin : 1;
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/**
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Ring voltage mode, specifies which voltage mode the processor will be operating.
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<b>0: Adaptive Mode</b> allows the processor to interpolate a voltage curve when beyond fused P0 range;
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1: Override, sets one voltage for for the entire frequency range, Pn-P0.
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**/
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UINT32 RingVoltageMode : 1;
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UINT32 GtVoltageMode : 1; ///< Specifies whether GT voltage is operating in Adaptive or Override mode: <b>0=Adaptive</b>, 1=Override
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UINT32 RealtimeMemoryTiming : 1; ///< Enable/Disable the message sent to the CPU to allow realtime memory timing changes after MRC_DONE. <b>0=Disable</b>, 1=Enable
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UINT32 FivrFaults : 1; ///< Fivr Faults. Enable or Disable FIVR Faults. 0: Disabled, <b>1: Enabled.</b>
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UINT32 FivrEfficiency : 1; ///< Fivr Efficiency Management. 0: Disabled, <b>1: Enabled.</b>
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/**
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Selects Core Voltage & Frequency Point Offset between Legacy and Selection modes.
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Need Reset System after enabling OverClocking Feature to Initialize the default value.
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<b>0: In Legacy Mode, setting a global offset for the entire VF curve.</b>
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1: In Selection modes, setting a selected VF point.
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**/
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UINT32 CoreVfPointOffsetMode : 1;
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UINT32 UnlimitedIccMax : 1; ///< Support Unlimited ICCMAX more than maximum value 255.75A. <b>0: Disabled</b>, 1: Enabled.
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UINT32 PerCoreRatioOverride : 1; ///< Enable or disable Per Core PState OC supported by writing OCMB 0x1D to program new favored core ratio to each Core. <b>0: Disable</b>, 1: enable
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UINT32 DynamicMemoryChange : 1; ///< Dynamic Memory Timings Changes; <b>0: Disabled</b>; 1: Enabled.
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UINT32 RsvdBits : 2; ///< Reserved for future use
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/**
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Maximum core turbo ratio override allows to increase CPU core frequency beyond the fused max turbo ratio limit (P0).
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<b>0. no override/HW defaults.</b>. Range 0-85.
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**/
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UINT8 CoreMaxOcRatio;
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UINT8 GtMaxOcRatio; ///< Maximum GT turbo ratio override: 0=Minimal, 60=Maximum, <b>0=AUTO</b>
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/**
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Maximum ring ratio override allows to increase CPU ring frequency beyond the fused max ring ratio limit.
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<b>0. no override/HW defaults.</b>. Range 0-85.
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**/
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UINT8 RingMaxOcRatio;
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UINT8 RsvdByte1;
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/**
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The core voltage override which is applied to the entire range of cpu core frequencies.
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Used when CoreVoltageMode = Override.
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<b>0. no override</b>. Range 0-2000 mV.
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**/
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UINT16 CoreVoltageOverride;
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/**
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Adaptive Turbo voltage target used to define the interpolation voltage point when the cpu is operating in turbo mode range.
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Used when CoreVoltageMode = Adaptive.
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<b>0. no override</b>. Range 0-2000mV.
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**/
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UINT16 CoreVoltageAdaptive;
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/**
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The core voltage offset applied on top of all other voltage modes. This offset is applied over the entire frequency range.
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This is a 2's complement number in mV units. <b>Default: 0</b> Range: -1000 to 1000.
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**/
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INT16 CoreVoltageOffset;
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/**
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The ring voltage override which is applied to the entire range of cpu ring frequencies.
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Used when RingVoltageMode = Override.
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<b>0. no override</b>. Range 0-2000 mV.
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**/
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UINT16 RingVoltageOverride;
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/**
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Adaptive Turbo voltage target used to define the interpolation voltage point when the ring is operating in turbo mode range.
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Used when RingVoltageMode = Adaptive.
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<b>0. no override</b>. Range 0-2000mV.
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**/
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UINT16 RingVoltageAdaptive;
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/**
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The ring voltage offset applied on top of all other voltage modes. This offset is applied over the entire frequency range.
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This is a 2's complement number in mV units. <b>Default: 0</b> Range: -1000 to 1000.
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**/
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INT16 RingVoltageOffset;
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INT16 GtVoltageOffset; ///< The voltage offset applied to GT slice. Valid range from -1000mv to 1000mv: <b>0=Minimal</b>, 1000=Maximum
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UINT16 GtVoltageOverride; ///< The GT voltage override which is applied to the entire range of GT frequencies <b>0=Default</b>
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UINT16 GtExtraTurboVoltage; ///< The adaptive voltage applied during turbo frequencies. Valid range from 0 to 2000mV: <b>0=Minimal</b>, 2000=Maximum
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INT16 SaVoltageOffset; ///< The voltage offset applied to the SA. Valid range from -1000mv to 1000mv: <b>0=Default</b>
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UINT32 GtPllVoltageOffset : 6; ///< GT PLL voltage offset. <b>0: No offset</b>. Range 0-63 in 17.5mv units.
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UINT32 RingPllVoltageOffset : 6; ///< Ring PLL voltage offset. <b>0: No offset</b>. Range 0-63 in 17.5mv units.
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UINT32 SaPllVoltageOffset : 6; ///< System Agent PLL voltage offset. <b>0: No offset</b>. Range 0-63 in 17.5mv units.
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UINT32 McPllVoltageOffset : 6; ///< Memory Controller PLL voltage offset. <b>0: No offset</b>. Range 0-63 in 17.5mv units.
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UINT32 RsvdBits1 : 8;
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/**
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TjMax Offset. Specified value here is clipped by pCode (125 - TjMax Offset) to support TjMax in the range of 62 to 115 deg Celsius.
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<b> Default: 0 Hardware Defaults </b> Range 10 to 63. 0 = No offset / Keep HW default.
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**/
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UINT8 TjMaxOffset;
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UINT8 RsvdByte2[3]; //< Reserved for dword alignment
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/**
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This service controls Core frequency reduction caused by high package temperatures for processors that
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implement the Intel Thermal Velocity Boost (TVB) feature. It is required to be disabled for supporting
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overclocking at frequencies higher than the default max turbo frequency.
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<b>0: Disables TVB ratio clipping. </b>1: Enables TVB ratio clipping.
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**/
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UINT32 TvbRatioClipping : 1;
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/**
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This service controls thermal based voltage optimizations for processors that implement the Intel
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Thermal Velocity Boost (TVB) feature.
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0: Disables TVB voltage optimization. <b>1: Enables TVB voltage optimization.</b>
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**/
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UINT32 TvbVoltageOptimization : 1;
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UINT32 RsvdBits2 : 30;
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/**
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Defines the per-core HT disable mask where: 1 - Disable selected logical core HT, 0 - is ignored.
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Input is in HEX and each bit maps to a logical core. Ex. A value of '1F' would disable HT for cores 4,3,2,1 and 0.
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<b>Default is 0</b>, all cores have HT enabled. Range is 0 - 0x1FF. You can only disable up to MAX_CORE_COUNT - 1.
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**/
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UINT16 PerCoreHtDisable;
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/**
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Avx2 Voltage Guardband Scale Factor
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This controls the AVX2 Voltage Guardband Scale factor applied to AVX2 workloads.
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Valid range is 0-200 in 1/100 units, where a value of 125 would apply a 1.25 scale factor.
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A value of 0 means no scale factor applied (no change to voltage on AVX commands)
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A value of 100 applies the default voltage guardband values (1.0 factor).
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A value > 100 will increase the voltage guardband on AVX2 workloads.
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A value < 100 will decrease the voltage guardband on AVX2 workloads.
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<b>0. No scale factor applied</b>
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**/
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UINT8 Avx2VoltageScaleFactor;
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/**
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Avx512 Voltage Guardband Scale Factor
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This controls the AVX512 Voltage Guardband Scale factor applied to AVX512 workloads.
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Valid range is 0-200 in 1/100 units, where a value of 125 would apply a 1.25 scale factor.
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A value of 0 means no scale factor applied (no change to voltage on AVX commands)
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A value of 100 applies the default voltage guardband values (1.0 factor).
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A value > 100 will increase the voltage guardband on AVX512 workloads.
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A value < 100 will decrease the voltage guardband on AVX512 workloads.
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<b>0. No scale factor applied</b>
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**/
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UINT8 Avx512VoltageScaleFactor;
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/**
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Array used to specifies the Core Voltage Offset applied to the each selected VF Point.
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This voltage is specified in millivolts.
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**/
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INT16 CoreVfPointOffset[CPU_OC_MAX_VF_POINTS];
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UINT8 RsvdByte3[2]; ///< Just to keep native alignment.
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/**
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Array for the each selected VF Point to display the Core Ration.
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**/
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UINT8 CoreVfPointRatio[CPU_OC_MAX_VF_POINTS];
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/**
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Number of supported Core Voltage & Frequency Point.
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**/
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UINT8 CoreVfPointCount;
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/**
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Core mask is a bitwise indication of which core should be disabled. Bit 0 - core 0, bit 7 - core 7.
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**/
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UINT32 DisableCoreMask;
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UINT8 PerCoreRatio[CPU_OC_MAX_CORES];
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/**
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The VcccIn voltage override.
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This will override VccIn output voltage level to the voltage value specified.
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The voltage level is fixed and will not change except on PKG C-states or resets.
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<b>0. no override</b>. Range 0-3000 mV.
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**/
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UINT32 VccInVoltageOverride;
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} OVERCLOCKING_PREMEM_CONFIG;
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#pragma pack (pop)
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#endif // _CPU_OVERCLOCKING_CONFIG_H_
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