/** @file
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Hybrid Graphics policy definitions
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Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _HYBRID_GRAPHICS_CONFIG_H_
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#define _HYBRID_GRAPHICS_CONFIG_H_
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#define HYBRID_GRAPHICS_CONFIG_REVISION 2
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#pragma pack(push, 1)
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///
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/// GPIO Support
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///
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typedef enum {
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NotSupported = 0,
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PchGpio,
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I2CGpio,
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} GPIO_SUPPORT;
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///
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/// CPU PCIe GPIO Data Structure
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///
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typedef struct {
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UINT8 ExpanderNo; ///< Offset 0 Expander No For I2C based GPIO
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BOOLEAN Active; ///< Offset 1 0=Active Low; 1=Active High
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UINT8 Rsvd0[2]; ///< Offset 2 Reserved
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UINT32 GpioNo; ///< Offset 4 GPIO pad
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} CPU_PCIE_GPIO_INFO;
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/**
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CPU PCIE RTD3 GPIO Data Structure
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**/
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typedef struct {
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CPU_PCIE_GPIO_INFO HoldRst; ///< Offset 0 This field contain PCIe HLD RESET GPIO value and level information
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CPU_PCIE_GPIO_INFO PwrEnable; ///< Offset 8 This field contain PCIe PWR Enable GPIO value and level information
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UINT32 WakeGpioNo; ///< Offset 16 This field contain PCIe RTD3 Device Wake GPIO Number
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UINT8 GpioSupport; ///< Offset 20 Depends on board design the GPIO configuration may be different: <b>0=Not Supported</b>, 1=PCH Based, 2=I2C based
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UINT8 Rsvd0[3]; ///< Offset 21
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} CPU_PCIE_RTD3_GPIO;
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/**
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This Configuration block configures CPU PCI Express 0/1/2 RTD3 GPIOs & Root Port.
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Hybrid Gfx uses the same GPIOs & Root port as PCI Express 0/1/2 RTD3.
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<b>Revision 1</b>:
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- Initial version.
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<b>Revision 2</b>:
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- Add HgSlot Policy: PEG or PCH Slot Slection for Hybrid Graphics
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**/
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typedef struct {
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CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
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CPU_PCIE_RTD3_GPIO CpuPcie0Rtd3Gpio; ///< Offset 28 RTD3 GPIOs used for PCIe
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UINT8 RootPortIndex; ///< Offset 52 Root Port Index number used for HG
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UINT8 HgMode; ///< Offset 53 HgMode: <b>0=Disabled</b>, 1=HG Muxed, 2=HG Muxless, 3=PEG
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UINT16 HgSubSystemId; ///< Offset 54 Hybrid Graphics Subsystem ID: <b>2212</b>
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UINT16 HgDelayAfterPwrEn; ///< Offset 56 Dgpu Delay after Power enable using Setup option: 0=Minimal, 1000=Maximum, <b>300=300 microseconds</b>
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UINT16 HgDelayAfterHoldReset; ///< Offset 58 Dgpu Delay after Hold Reset using Setup option: 0=Minimal, 1000=Maximum, <b>100=100 microseconds</b>
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CPU_PCIE_RTD3_GPIO CpuPcie1Rtd3Gpio; ///< Offset 60 RTD3 GPIOs used for PCIe
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CPU_PCIE_RTD3_GPIO CpuPcie2Rtd3Gpio; ///< Offset 84 RTD3 GPIOs used for PCIe
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CPU_PCIE_RTD3_GPIO CpuPcie3Rtd3Gpio; ///< Offset 108 RTD3 GPIOs used for PCIe
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UINT8 HgSlot; ///< Offset 132 Slot selection between PEG and PCH
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UINT8 Rsvd0[3]; ///< Offset 133 Reserved Bytes
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} HYBRID_GRAPHICS_CONFIG;
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#pragma pack(pop)
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#endif // _HYBRID_GRAPHICS_CONFIG_H_
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