/** @file
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Espi policy
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Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _ESPI_CONFIG_H_
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#define _ESPI_CONFIG_H_
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#define ESPI_CONFIG_REVISION 2
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extern EFI_GUID gEspiConfigGuid;
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#pragma pack (push,1)
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/**
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This structure contains the policies which are related to ESPI.
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<b>Revision 1</b>:
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- Initial revision
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<b>Revision 2</b>:
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- Added LockLinkConfiguration field to config block
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**/
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typedef struct {
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CONFIG_BLOCK_HEADER Header; ///< Config Block Header
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/**
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LPC (eSPI) Memory Range Decode Enable. When TRUE, then the range
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specified in PCLGMR[31:16] is enabled for decoding to LPC (eSPI).
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<b>0: FALSE</b>, 1: TRUE
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**/
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UINT32 LgmrEnable : 1;
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/**
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eSPI Master and Slave BME settings.
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When TRUE, then the BME bit enabled in eSPI Master and Slave.
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0: FALSE, <b>1: TRUE </b>
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**/
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UINT32 BmeMasterSlaveEnabled : 1;
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/**
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Master HOST_C10 (Virtual Wire) to Slave Enable (VWHC10OE)
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<b>0b: Disable HOST_C10 reporting (HOST_C10 indication from PMC is ignored)</b>
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1b: Enable HOST_C10 reporting to Slave via eSPI Virtual Wire (upon receiving a HOST_C10 indication from PMC)
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**/
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UINT32 HostC10ReportEnable : 1;
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/**
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eSPI Link Configuration Lock (SBLCL)
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If set to TRUE then communication through SET_CONFIG/GET_CONFIG
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to eSPI slaves addresses from range 0x0 - 0x7FF
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<b>1: TRUE</b>, 0: FALSE
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**/
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UINT32 LockLinkConfiguration : 1;
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/**
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Hardware Autonomous Enable (HAE)
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If set to TRUE, then the IP may request a PG whenever it is idle
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**/
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UINT32 EspiPmHAE : 1;
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UINT32 RsvdBits : 27; ///< Reserved bits
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} PCH_ESPI_CONFIG;
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#pragma pack (pop)
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#endif // _ESPI_CONFIG_H_
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