/** @file
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DMI policy
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Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _CPU_DMI_PREMEM_CONFIG_H_
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#define _CPU_DMI_PREMEM_CONFIG_H_
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#include <ConfigBlock.h>
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#include <Register/SaRegsHostBridge.h>
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#define DMI_CONFIG_REVISION 1
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#define CPU_DMI_HWEQ_COEFFS_MAX 8
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#pragma pack (push,1)
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///
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/// The values before AutoConfig match the setting of PCI Express Base Specification 1.1, please be careful for adding new feature
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///
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typedef enum {
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DmiAspmDisabled,
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DmiAspmL0s,
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DmiAspmL1,
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DmiAspmL0sL1,
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DmiAspmAutoConfig,
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DmiAspmMax
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} DMI_ASPM;
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/**
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The CPU_DMI_CONFIG block describes the expected configuration of the CPU for DMI.
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<b>Revision 1</b>:
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- Initial version.
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**/
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typedef struct {
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CONFIG_BLOCK_HEADER Header; ///< Config Block Header
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/**
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- <b>Auto</b> (0x0) : Maximum possible link speed (Default)
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- Gen1 (0x1) : Limit Link to Gen1 Speed
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- Gen2 (0x2) : Limit Link to Gen2 Speed CpuDmiPreMemConfig
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- Gen3 (0x3) : Limit Link to Gen3 Speed
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**/
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UINT8 DmiMaxLinkSpeed;
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/**
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<b>(Test)</b> DMI Equalization Phase 2 Enable Control
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- Disabled (0x0) : Disable phase 2
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- Enabled (0x1) : Enable phase 2
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- <b>Auto</b> (0x2) : Use the current default method (Default)
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**/
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UINT8 DmiGen3EqPh2Enable;
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/**
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<b>(Test)</b> Selects the method for performing Phase3 of Gen3 Equalization on DMI
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- <b>Auto</b> (0x0) : Use the current default method (Default)
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- HwEq (0x1) : Use Adaptive Hardware Equalization
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- SwEq (0x2) : Use Adaptive Software Equalization (Implemented in BIOS Reference Code)
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- Static (0x3) : Use the Static EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just Phase1)
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- Disabled (0x4) : Bypass Equalization Phase 3
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**/
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UINT8 DmiGen3EqPh3Method;
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/**
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<b>(Test)</b> Program DMI Gen3 EQ Phase1 Static Presets
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- Disabled (0x0) : Disable EQ Phase1 Static Presets Programming
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- <b>Enabled</b> (0x1) : Enable EQ Phase1 Static Presets Programming (Default)
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**/
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UINT8 DmiGen3ProgramStaticEq;
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UINT8 DmiDeEmphasis; ///< DeEmphasis control for DMI (-6 dB and -3.5 dB are the options)
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UINT8 DmiAspm;
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UINT8 DmiAspmCtrl; ///< ASPM configuration on the CPU side of the DMI/OPI Link. Default is <b>DmiAspmAutoConfig</b>
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UINT8 DmiAspmL1ExitLatency; ///< ASPM configuration on the CPU side of the DMI/OPI Link. Default is <b>DmiAspmAutoConfig</b>
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UINT8 DmiGen3RootPortPreset[SA_DMI_MAX_LANE]; ///< Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane
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UINT8 DmiGen3EndPointPreset[SA_DMI_MAX_LANE]; ///< Used for programming DMI Gen3 preset values per lane. Range: 0-9, 7 is default for each lane
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UINT8 DmiGen3EndPointHint[SA_DMI_MAX_LANE]; ///< Hint value per lane for the DMI Gen3 End Point. Range: 0-6, 2 is default for each lane
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/**
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DMI Gen3 RxCTLEp per-Bundle control. The range of the setting is (0-15). This setting
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has to be specified based upon platform design and must follow the guideline. Default is 12.
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**/
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UINT8 DmiGen3RxCtlePeaking[SA_DMI_MAX_BUNDLE];
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} CPU_DMI_PREMEM_CONFIG;
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#pragma pack (pop)
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#endif // _CPU_DMI_CONFIG_H_
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