/** @file
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Header file for TigerLake PCH devices PCI Bus Device Function map.
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Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _PCH_BDF_ASSIGNMENT_H_
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#define _PCH_BDF_ASSIGNMENT_H_
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#define NOT_PRESENT 0xFF
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#define MAX_SATA_CONTROLLER 1
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//
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// PCH PCIe Controllers
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//
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#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_1 28
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#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_2 28
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#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_3 28
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#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_4 28
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#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_5 28
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#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_6 28
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#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_7 28
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#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_8 28
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#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_9 29
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#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_10 29
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#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_11 29
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#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_12 29
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#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_13 29
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#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_14 29
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#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_15 29
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#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_16 29
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#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_17 27
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#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_18 27
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#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_19 27
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#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_20 27
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#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_21 27
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#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_22 27
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#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_23 27
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#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_24 27
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#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_25 NOT_PRESENT
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#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_26 NOT_PRESENT
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#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_27 NOT_PRESENT
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#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_28 NOT_PRESENT
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//
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// USB3 (XHCI) Controller PCI config
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//
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#define PCI_DEVICE_NUMBER_PCH_XHCI 20
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#define PCI_FUNCTION_NUMBER_PCH_XHCI 0
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//
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// xDCI (OTG) USB Device Controller
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//
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#define PCI_DEVICE_NUMBER_PCH_XDCI 20
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#define PCI_FUNCTION_NUMBER_PCH_XDCI 1
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//
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// Thermal Device
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//
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#define PCI_DEVICE_NUMBER_PCH_THERMAL NOT_PRESENT
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#define PCI_FUNCTION_NUMBER_PCH_THERMAL NOT_PRESENT
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//
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// CSME HECI #1
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//
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#define PCI_DEVICE_NUMBER_PCH_HECI1 22
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#define PCI_FUNCTION_NUMBER_PCH_HECI1 0
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//
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// CSME HECI #2
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//
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#define PCI_DEVICE_NUMBER_PCH_HECI2 22
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#define PCI_FUNCTION_NUMBER_PCH_HECI2 1
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//
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// CSME IDE-Redirection (IDE-R)
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//
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#define PCI_DEVICE_NUMBER_PCH_IDER 22
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#define PCI_FUNCTION_NUMBER_PCH_IDER 2
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//
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// CSME Keyboard and Text (KT) Redirection
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//
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#define PCI_DEVICE_NUMBER_PCH_KTR 22
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#define PCI_FUNCTION_NUMBER_PCH_KTR 3
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//
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// CSME HECI #3
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//
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#define PCI_DEVICE_NUMBER_PCH_HECI3 22
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#define PCI_FUNCTION_NUMBER_PCH_HECI3 4
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//
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// CSME HECI #4
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//
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#define PCI_DEVICE_NUMBER_PCH_HECI4 22
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#define PCI_FUNCTION_NUMBER_PCH_HECI4 5
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//
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// CSME MROM
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//
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#define PCI_DEVICE_NUMBER_PCH_MROM NOT_PRESENT
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#define PCI_FUNCTION_NUMBER_PCH_MROM NOT_PRESENT
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//
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// CSME WLAN
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//
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#define PCI_DEVICE_NUMBER_PCH_WLAN 22
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#define PCI_FUNCTION_NUMBER_PCH_WLAN 7
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//
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// SATA Controllers
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//
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#define PCI_DEVICE_NUMBER_PCH_SATA_1 23
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#define PCI_FUNCTION_NUMBER_PCH_SATA_1 0
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#define PCI_DEVICE_NUMBER_PCH_SATA_2 NOT_PRESENT
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#define PCI_FUNCTION_NUMBER_PCH_SATA_2 NOT_PRESENT
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#define PCI_DEVICE_NUMBER_PCH_SATA_3 NOT_PRESENT
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#define PCI_FUNCTION_NUMBER_PCH_SATA_3 NOT_PRESENT
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//
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// PCH LP Serial IO I2C #0 Controller
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//
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#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C0 21
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#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C0 0
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//
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// PCH LP Serial IO I2C #1 Controller
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//
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#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C1 21
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#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C1 1
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//
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// PCH LP Serial IO I2C #2 Controller
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//
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#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C2 21
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#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C2 2
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//
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// PCH LP Serial IO I2C #3 Controller
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//
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#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C3 21
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#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C3 3
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//
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// PCH LP Serial IO I2C #4 Controller
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//
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#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C4 25
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#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C4 0
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//
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// PCH LP Serial IO I2C #5 Controller
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//
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#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C5 25
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#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C5 1
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//
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// PCH LP Serial IO I2C #6 Controller
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//
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#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C6 16
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#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C6 0
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//
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// PCH LP Serial IO I2C #7 Controller
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//
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#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C7 16
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#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C7 1
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//
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// PCH LP Serial IO SPI #0 Controller
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//
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#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_SPI0 30
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#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI0 2
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//
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// PCH LP Serial IO SPI #1 Controller
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//
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#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_SPI1 30
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#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI1 3
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//
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// PCH LP Serial IO SPI #2 Controller
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//
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#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_SPI2 18
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#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI2 6
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//
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// PCH LP Serial IO SPI #3 Controller
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//
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#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_SPI3 19
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#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI3 0
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//
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// PCH LP Serial IO SPI #4 Controller
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//
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#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_SPI4 19
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#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI4 1
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//
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// PCH LP Serial IO SPI #5 Controller
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//
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#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_SPI5 19
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#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI5 2
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//
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// PCH LP Serial IO SPI #6 Controller
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//
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#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_SPI6 19
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#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI6 3
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//
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// PCH LP Serial IO UART #0 Controller
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//
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#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART0 30
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#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART0 0
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//
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// PCH LP Serial IO UART #1 Controller
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//
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#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART1 30
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#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART1 1
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//
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// PCH LP Serial IO UART #2 Controller
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//
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#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART2 25
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#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART2 2
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//
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// PCH LP Serial IO UART #3 Controller
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//
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#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART3 17
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#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART3 0
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//
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// PCH LP Serial IO UART #4 Controller
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//
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#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART4 17
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#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART4 1
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//
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// PCH LP Serial IO UART #5 Controller
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//
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#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART5 17
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#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART5 2
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//
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// PCH LP Serial IO UART #6 Controller
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//
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#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART6 17
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#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART6 3
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//
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// DMA-SMBus Controller
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//
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#define PCI_DEVICE_NUMBER_PCH_DMA_SMBUS 30
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#define PCI_FUNCTION_NUMBER_PCH_DMA_SMBUS 4
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//
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// TSN GbE Controller #1
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//
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#define PCI_DEVICE_NUMBER_PCH_TSN0 30
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#define PCI_FUNCTION_NUMBER_PCH_TSN0 4
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//
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// TSN GbE Controller #2
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//
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#define PCI_DEVICE_NUMBER_PCH_TSN1 30
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#define PCI_FUNCTION_NUMBER_PCH_TSN1 5
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//
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// LPC Controller
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//
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#define PCI_DEVICE_NUMBER_PCH_LPC 31
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#define PCI_FUNCTION_NUMBER_PCH_LPC 0
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//
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// eSPI Controller
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//
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#define PCI_DEVICE_NUMBER_PCH_ESPI 31
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#define PCI_FUNCTION_NUMBER_PCH_ESPI 0
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//
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// Primary to Sideband (P2SB) Bridge
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//
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#define PCI_DEVICE_NUMBER_PCH_P2SB 31
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#define PCI_FUNCTION_NUMBER_PCH_P2SB 1
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//
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// PMC (D31:F2)
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//
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#define PCI_DEVICE_NUMBER_PCH_PMC 31
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#define PCI_FUNCTION_NUMBER_PCH_PMC 2
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//
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// PMC SSRAM Registers
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//
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#define PCI_DEVICE_NUMBER_PCH_PMC_SSRAM 20
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#define PCI_FUNCTION_NUMBER_PCH_PMC_SSRAM 2
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//
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// HD-A Controller
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//
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#define PCI_DEVICE_NUMBER_PCH_HDA 31
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#define PCI_FUNCTION_NUMBER_PCH_HDA 3
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//
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// SMBus Controller
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//
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#define PCI_DEVICE_NUMBER_PCH_SMBUS 31
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#define PCI_FUNCTION_NUMBER_PCH_SMBUS 4
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//
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// SPI Controller (D31:F5)
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//
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#define PCI_DEVICE_NUMBER_PCH_SPI 31
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#define PCI_FUNCTION_NUMBER_PCH_SPI 5
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//
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// Gigabit Ethernet LAN Controller (D31:F6)
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//
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#define PCI_DEVICE_NUMBER_GBE 31
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#define PCI_FUNCTION_NUMBER_GBE 6
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#endif // _PCH_BDF_ASSIGNMENT_H_
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