/** @file
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CPU PCIe information library.
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All function in this library is available for PEI, DXE, and SMM,
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But do not support UEFI RUNTIME environment call.
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Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Uefi/UefiBaseType.h>
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#include <Library/DebugLib.h>
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#include <Library/BaseLib.h>
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#include <Library/PciSegmentLib.h>
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#include <Register/CpuPcieRegs.h>
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#include <Library/CpuPcieInfoFruLib.h>
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#include <Library/CpuPcieInitCommon.h>
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#include <CpuPcieInfo.h>
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#include <Register/SaRegsHostBridge.h>
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#include <PcieRegs.h>
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/**
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Get Maximum CPU Pcie Root Port Number
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@retval Maximum CPU Pcie Root Port Number
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**/
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UINT8
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GetMaxCpuPciePortNum (
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VOID
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)
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{
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return CPU_PCIE_ULT_ULX_MAX_ROOT_PORT;
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}
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/**
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Get CPU Pcie Root Port Device and Function Number by Root Port physical Number
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@param[in] RpNumber Root port physical number. (0-based)
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@param[out] RpDev Return corresponding root port device number.
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@param[out] RpFun Return corresponding root port function number.
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@retval EFI_SUCCESS Root port device and function is retrieved
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@retval EFI_INVALID_PARAMETER RpNumber is invalid
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**/
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EFI_STATUS
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EFIAPI
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GetCpuPcieRpDevFun (
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IN UINTN RpNumber,
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OUT UINTN *RpDev,
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OUT UINTN *RpFun
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)
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{
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if (RpNumber > GetMaxCpuPciePortNum ()) {
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DEBUG ((DEBUG_ERROR, "GetCpuPcieRpDevFun invalid RpNumber %x", RpNumber));
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ASSERT (FALSE);
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return EFI_INVALID_PARAMETER;
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}
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//
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// For TGL - U/Y only one CPU PCIE Root port is present
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//
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*RpDev = 6;
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*RpFun = 0;
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return EFI_SUCCESS;
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}
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/**
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Gets pci segment base address of PCIe root port.
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@param RpIndex Root Port Index (0 based)
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@return PCIe port base address.
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**/
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UINT64
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CpuPcieBase (
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IN UINT32 RpIndex
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)
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{
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UINTN RpDevice;
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UINTN RpFunction;
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GetCpuPcieRpDevFun (RpIndex, &RpDevice, &RpFunction);
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return PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, SA_MC_BUS, (UINT32) RpDevice, (UINT32) RpFunction, 0);
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}
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