/** @file
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CPU Power Management Test Config Block.
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Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _CPU_POWER_MGMT_TEST_CONFIG_H_
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#define _CPU_POWER_MGMT_TEST_CONFIG_H_
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#define CPU_POWER_MGMT_TEST_CONFIG_REVISION 4
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extern EFI_GUID gCpuPowerMgmtTestConfigGuid;
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#pragma pack (push,1)
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///
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/// PPM Package C State Limit
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///
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typedef enum {
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PkgC0C1 = 0,
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PkgC2,
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PkgC3,
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PkgC6,
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PkgC7,
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PkgC7s,
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PkgC8,
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PkgC9,
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PkgC10,
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PkgCMax,
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PkgCpuDefault = 254,
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PkgAuto = 255
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} MAX_PKG_C_STATE;
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///
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/// PPM Package C State Time Limit
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///
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typedef enum {
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TimeUnit1ns = 0,
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TimeUnit32ns,
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TimeUnit1024ns,
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TimeUnit32768ns,
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TimeUnit1048576ns,
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TimeUnit33554432ns,
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TimeUnitMax
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} C_STATE_TIME_UNIT;
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///
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/// Custom Power Units. User can choose to enter in watts or 125 milliwatt increments.
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///
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typedef enum {
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PowerUnitWatts = 0, ///< in Watts.
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PowerUnit125MilliWatts, ///< in 125 milliwatt increments. Example: 90 power units times 125 mW equals 11.250 W.
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PowerUnitMax
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} CUSTOM_POWER_UNIT;
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///
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/// PPM Interrupt Redirection Mode Selection
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///
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typedef enum {
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PpmIrmFixedPriority = 0,
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PpmIrmRoundRobin,
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PpmIrmHashVector,
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PpmIrmReserved1,
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PpmIrmReserved2,
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PpmIrmReserved3,
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PpmIrmReserved4,
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PpmIrmNoChange
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} PPM_IRM_SETTING;
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/**
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CPU Power Management Test Configuration Structure.
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<b>Revision 1</b>:
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- Initial version.
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<b>Revision 2</b>:
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- Add CstateLatencyControl0TimeUnit for WHL only
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- Add CstateLatencyControl0Irtl for WHL only
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<b>Revision 3</b>:
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- Change C State LatencyContol to Auto as default.
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<b>Revision 4</b>:
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- Deprecate ConfigTdpLevel. Move to premem.
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**/
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typedef struct {
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CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
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UINT32 Eist : 1; ///< Offset 28-31 Enable or Disable Intel SpeedStep Technology. 0: Disable; <b>1: Enable</b>
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UINT32 EnergyEfficientPState : 1; ///< Enable or Disable Energy Efficient P-state will be applied in Turbo mode. Disable; <b>1: Enable</b>
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UINT32 EnergyEfficientTurbo : 1; ///< Enable or Disable Energy Efficient Turbo, will be applied in Turbo mode. Disable; <b>1: Enable</b>
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UINT32 TStates : 1; ///< Enable or Disable T states; <b>0: Disable</b>; 1: Enable.
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UINT32 BiProcHot : 1; ///< Enable or Disable Bi-Directional PROCHOT#; 0: Disable; <b>1: Enable</b>.
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UINT32 DisableProcHotOut : 1; ///< Enable or Disable PROCHOT# signal being driven externally; 0: Disable; <b>1: Enable</b>.
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UINT32 ProcHotResponse : 1; ///< Enable or Disable PROCHOT# Response; <b>0: Disable</b>; 1: Enable.
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UINT32 DisableVrThermalAlert : 1; ///< Enable or Disable VR Thermal Alert; <b>0: Disable</b>; 1: Enable.
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UINT32 EnableAllThermalFunctions : 1; ///< Enable or Disable Thermal Reporting through ACPI tables; 0: Disable; <b>1: Enable</b>.
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UINT32 ThermalMonitor : 1; ///< Enable or Disable Thermal Monitor; 0: Disable; <b>1: Enable</b>.
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UINT32 Cx : 1; ///< Enable or Disable CPU power states (C-states). 0: Disable; <b>1: Enable</b>
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UINT32 PmgCstCfgCtrlLock : 1; ///< If enabled, sets MSR 0xE2[15]; 0: Disable; <b>1: Enable</b>.
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UINT32 C1e : 1; ///< Enable or Disable Enhanced C-states. 0: Disable; <b>1: Enable</b>
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UINT32 C1AutoDemotion : 1; ///< Enable or Disable C6/C7 auto demotion to C1. 0: Disabled; <b>1: C1 Auto demotion</b>
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UINT32 C1UnDemotion : 1; ///< Enable or Disable C1UnDemotion. 0: Disabled; <b>1: C1 Auto undemotion</b>
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UINT32 C3AutoDemotion : 1; ///< [CoffeeLake Only] Enable or Disable C6/C7 auto demotion to C3 0: Disabled; <b>1: C3 Auto demotion</b>
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UINT32 C3UnDemotion : 1; ///< [CoffeeLake Only] Enable or Disable C3UnDemotion. 0: Disabled; <b>1: C3 Auto undemotion</b>
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UINT32 PkgCStateDemotion : 1; ///< Enable or Disable Package Cstate Demotion. Disable; <b>1: Enable</b> [WhiskeyLake] <b>Disable</b>; 1: Enable
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UINT32 PkgCStateUnDemotion : 1; ///< Enable or Disable Package Cstate UnDemotion. Disable; <b>1: Enable</b> [WhiskeyLake] <b>Disable</b>; 1: Enable
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UINT32 CStatePreWake : 1; ///< Enable or Disable CState-Pre wake. Disable; <b>1: Enable</b>
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UINT32 TimedMwait : 1; ///< Enable or Disable TimedMwait Support. <b>Disable</b>; 1: Enable
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UINT32 CstCfgCtrIoMwaitRedirection : 1; ///< Enable or Disable IO to MWAIT redirection; <b>0: Disable</b>; 1: Enable.
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UINT32 ProcHotLock : 1; ///< If enabled, sets MSR 0x1FC[23]; <b>0: Disable</b>; 1: Enable.
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UINT32 RaceToHalt : 1; ///< Enable or Disable Race To Halt feature; 0: Disable; <b>1: Enable </b>. RTH will dynamically increase CPU frequency in order to enter pkg C-State faster to reduce overall power. (RTH is controlled through MSR 1FC bit 20)
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UINT32 ConfigTdpLevel : 8; ///< @deprecated. Move to premem phase.
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UINT16 CstateLatencyControl1Irtl; ///< Offset 32-33 Interrupt Response Time Limit of LatencyContol1 MSR 0x60B[9:0].<b>0 is Auto</b>.
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UINT16 CstateLatencyControl2Irtl; ///< Offset 34-35 Interrupt Response Time Limit of LatencyContol2 MSR 0x60C[9:0].<b>0 is Auto</b>.
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UINT16 CstateLatencyControl3Irtl; ///< Offset 36-37 Interrupt Response Time Limit of LatencyContol3 MSR 0x633[9:0].<b>0 is Auto</b>.
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UINT16 CstateLatencyControl4Irtl; ///< Offset 38-39 Interrupt Response Time Limit of LatencyContol4 MSR 0x634[9:0].<b>0 is Auto</b>.
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UINT16 CstateLatencyControl5Irtl; ///< Offset 40-41 Interrupt Response Time Limit of LatencyContol5 MSR 0x635[9:0].<b>0 is Auto</b>.
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// Due to the removal of CstateLatencyControl0Irtl, PkgCStateLimit is not aligned to 32-bit address.
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UINT8 Rsvd1[2]; ///< Offset 42-43 Reserved for config block alignment.
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MAX_PKG_C_STATE PkgCStateLimit; ///< Offset 44 This field is used to set the Max Pkg Cstate. Default set to Auto which limits the Max Pkg Cstate to deep C-state.
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/**
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@todo: The following enums have to be replaced with policies.
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**/
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C_STATE_TIME_UNIT Reserved; ///< Offset 45 Reserved for config block alignment.
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C_STATE_TIME_UNIT CstateLatencyControl1TimeUnit; ///< Offset 46 TimeUnit for Latency Control1 MSR 0x60B[12:10]; <b>2: 1024ns</b>.
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C_STATE_TIME_UNIT CstateLatencyControl2TimeUnit; ///< Offset 47 TimeUnit for Latency Control2 MSR 0x60C[12:10]; <b>2: 1024ns</b>.
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C_STATE_TIME_UNIT CstateLatencyControl3TimeUnit; ///< Offset 48 TimeUnit for Latency Control3 MSR 0x633[12:10]; <b>2: 1024ns</b>.
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C_STATE_TIME_UNIT CstateLatencyControl4TimeUnit; ///< Offset 49 TimeUnit for Latency Control4 MSR 0x634[12:10]; <b>2: 1024ns</b>.
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C_STATE_TIME_UNIT CstateLatencyControl5TimeUnit; ///< Offset 50 TimeUnit for Latency Control5 MSR 0x635[12:10]; <b>2: 1024ns</b>.
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/**
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Offset 51 Default power unit in watts or in 125 milliwatt increments.
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- 0: PowerUnitWatts.
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- <b>1: PowerUnit125MilliWatts</b>.
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**/
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CUSTOM_POWER_UNIT CustomPowerUnit;
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/**
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Offset 52 Interrupt Redirection Mode Select.
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- 0: Fixed priority. //Default under CNL.
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- 1: Round robin.
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- 2: Hash vector.
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- 4: PAIR with fixed priority. //Default under KBL, not available under CNL.
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- 5: PAIR with round robin. //Not available under CNL.
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- 6: PAIR with hash vector. //Not available under CNL.
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- 7: No change.
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**/
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PPM_IRM_SETTING PpmIrmSetting;
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// Move the padding to previous offset to align the structure at 32-bit address.
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UINT8 Rsvd[4]; ///< Offset 53-56 Reserved for future use and config block alignment
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} CPU_POWER_MGMT_TEST_CONFIG;
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#pragma pack (pop)
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#endif // _CPU_POWER_MGMT_TEST_CONFIG_H_
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