/** @file
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CPU Power Management Psys(Platform) Config Block.
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Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _CPU_POWER_MGMT_PSYS_CONFIG_H_
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#define _CPU_POWER_MGMT_PSYS_CONFIG_H_
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#define CPU_POWER_MGMT_PSYS_CONFIG_REVISION 1
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extern EFI_GUID gCpuPowerMgmtPsysConfigGuid;
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#pragma pack (push,1)
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/**
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CPU Power Management Psys(Platform) Configuration Structure.
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<b>Revision 1</b>:
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- Initial version.
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**/
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typedef struct {
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CONFIG_BLOCK_HEADER Header; ///< Config Block Header
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UINT32 PsysPowerLimit1 : 1; ///< MSR 0x65C[15]: PL1 Enable activates the PL1 value to limit average platform power
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UINT32 PsysPowerLimit1Time : 8; ///< MSR 0x65C[23:17]: PL1 timewindow in seconds.
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UINT32 PsysPowerLimit2 : 1; ///< MSR 0x65C[47]: PL2 Enable activates the PL2 value to limit average platform power
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UINT32 RsvdBits : 22; ///< Reserved for future use.
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UINT16 PsysPowerLimit1Power; ///< MSR 0x65C[14:0]: Platform PL1 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
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UINT16 PsysPowerLimit2Power; ///< MSR 0x65C[46:32]]: Platform PL2 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
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UINT16 PsysPmax; ///< PCODE MMIO Mailbox: Platform Power Pmax. <b>0 - Auto</b> Specified in 1/8 Watt increments. 0-1024 Watts. Value of 800 = 100W.
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UINT8 Rsvd[2]; ///< Reserved for future use and config block alignment
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} CPU_POWER_MGMT_PSYS_CONFIG;
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#pragma pack (pop)
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#endif // _CPU_POWER_MGMT_PSYS_CONFIG_H_
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