/** @file
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Various register numbers and value bits based on the following publications:
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- Intel(R) datasheet 319973-003
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- Intel(R) datasheet 319974-017US
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Copyright (C) 2015, Red Hat, Inc.
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Copyright (c) 2014, Gabriel L. Somlo <somlo@cmu.edu>
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Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef __X58_ICH10_H__
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#define __X58_ICH10_H__
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#include <Library/PciLib.h>
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#include <IndustryStandard/Pci22.h>
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//
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// Simics Host Bridge DID Address
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//
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#define SIMICS_HOSTBRIDGE_DID \
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PCI_LIB_ADDRESS (0, 0, 0, PCI_DEVICE_ID_OFFSET)
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//
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// Host Bridge Device ID (DID) value for ICH10
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//
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#define INTEL_ICH10_DEVICE_ID 0x3400
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//
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// B/D/F/Type: 0/0/0/PCI
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//
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#define DRAMC_REGISTER_Q35(Offset) PCI_LIB_ADDRESS (0, 0, 0, (Offset))
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#define DRAMC_REGISTER_X58(Offset) PCI_LIB_ADDRESS (0, 20, 0, (Offset))
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#define MCH_GGC 0x52
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#define MCH_GGC_IVD BIT1
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#define MCH_PCIEXBAR_LOW 0x10C
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#define MCH_PCIEXBAR_LID 0x10E
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#define MCH_PCIEXBAR_SHIFT 16
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#define MCH_PCIEXBAR_LOWMASK 0x0FFFFFFF
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#define MCH_PCIEXBAR_BUS_FF 0
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#define MCH_PCIEXBAR_EN BIT0
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#define MCH_PCIEXBAR_HIGH 0x64
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#define MCH_PCIEXBAR_HIGHMASK 0xFFFFFFF0
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#define MCH_SMRAM 0x9D
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#define MCH_SMRAM_D_LCK BIT4
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#define MCH_SMRAM_G_SMRAME BIT3
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#define MCH_ESMRAMC 0x9E
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#define MCH_ESMRAMC_H_SMRAME BIT7
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#define MCH_ESMRAMC_E_SMERR BIT6
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#define MCH_ESMRAMC_SM_CACHE BIT5
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#define MCH_ESMRAMC_SM_L1 BIT4
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#define MCH_ESMRAMC_SM_L2 BIT3
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#define MCH_ESMRAMC_TSEG_8MB BIT3
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#define MCH_ESMRAMC_TSEG_2MB BIT2
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#define MCH_ESMRAMC_TSEG_1MB BIT1
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#define MCH_ESMRAMC_TSEG_MASK (BIT3 | BIT2 | BIT1)
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#define MCH_ESMRAMC_T_EN BIT0
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#define MCH_GBSM 0xA4
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#define MCH_GBSM_MB_SHIFT 20
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#define MCH_BGSM 0xA8
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#define MCH_BGSM_MB_SHIFT 20
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#define MCH_TSEGMB 0xA8
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#define MCH_TSEGMB_MB_SHIFT 20
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#define MCH_TOLUD 0xD0
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//
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// B/D/F/Type: 0/0x1f/0/PCI
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//
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#define POWER_MGMT_REGISTER_ICH10(Offset) \
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PCI_LIB_ADDRESS (0, 0x1f, 0, (Offset))
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#define ICH10_PMBASE 0x40
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#define ICH10_PMBASE_MASK (BIT15 | BIT14 | BIT13 | BIT12 | BIT11 | \
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BIT10 | BIT9 | BIT8 | BIT7)
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#define ICH10_ACPI_CNTL 0x44
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#define ICH10_ACPI_CNTL_ACPI_EN BIT7
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#define ICH10_GEN_PMCON_1 0xA0
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#define ICH10_GEN_PMCON_1_SMI_LOCK BIT4
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#define ICH10_RCBA 0xF0
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#define ICH10_RCBA_EN BIT0
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#define ICH10_PMBASE_IO 0x400
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//
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// IO ports
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//
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#define ICH10_APM_CNT 0xB2
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#define ICH10_APM_STS 0xB3
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//
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// IO ports relative to PMBASE
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//
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#define ICH10_PMBASE_OFS_SMI_EN 0x30
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#define ICH10_SMI_EN_APMC_EN BIT5
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#define ICH10_SMI_EN_GBL_SMI_EN BIT0
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#define ICH10_SMI_EN_EOS BIT1 // End of SMI
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#define ICH10_PMBASE_OFS_SMI_STS 0x34
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#define ICH10_SMI_STS_APM BIT5 // APM Status
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#define ICH10_ROOT_COMPLEX_BASE 0xFED1C000
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#endif
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